PIC18F46J50-I/PT Microchip Technology, PIC18F46J50-I/PT Datasheet - Page 134

• Manufacturer Part Number: PIC18F46J50-I/PT
• Description: IC PIC MCU FLASH 64KB 44-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46J50-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 22
• Ram Memory Size: 3.6875KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• No. Of Pwm Channels: 2
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Interface Type: I2C/SPI/USART/USB
• On-chip Adc: 13-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164330 - MODULE SKT FOR 44TQFP 18F45J10
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F46J50 FAMILY
TABLE 9-5:
DS39931C-page 134
RB4/KBI0/
AN11/RP7/
SCK1/SCL1
RB5/KBI1/
SDI1/SDA1/
RP8
RB6/KBI2/
PGC/RP9
RB7/KBI3/
PGD/RP10
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
Note 1:
Pin
2:
input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog
inputs by default when PBADEN is set and digital inputs when PBADEN is cleared.
All other pin functions are disabled when ICSP™ or ICD are enabled.
PORTB I/O SUMMARY (CONTINUED)
Function
SCK1
SDA1
AN11
SCL1
RP10
SDI1
KBI0
KBI1
KBI2
PGC
KBI3
PGD
RB4
RP7
RB5
RP8
RB6
RP9
RB7
Setting
TRIS
0
1
1
1
1
0
1
0
1
0
0
1
1
1
1
0
1
0
0
1
1
x
1
0
0
1
1
x
x
1
0
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ST/TTL Parallel Master Port io_addr_in<1>.
SMBus
SMBus
Type
ANA
DIG
TTL
TTL
DIG
DIG
I
DIG
DIG
TTL
TTL
I
DIG
DIG
DIG
TTL
TTL
DIG
DIG
TTL
TTL
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
2
2
C/
C/
LATB<4> data output; not affected by analog input.
PORTB<4> data input; weak pull-up when RBPU bit is
cleared. Disabled when analog input enabled.
Interrupt-on-change pin.
A/D input channel 11.
Remappable peripheral pin 7 input.
Remappable peripheral pin 7 output.
Parallel Master Port address.
I
I
LATB<5> data output.
PORTB<5> data input; weak pull-up when RBPU bit is
cleared.
Interrupt-on-change pin.
SPI Data Input (MSSP1 module).
I
I
Remappable peripheral pin 8 input.
Remappable peripheral pin 8 output.
LATB<6> data output.
PORTB<6> data input; weak pull-up when RBPU bit is
cleared.
Interrupt-on-change pin.
Serial execution (ICSP™) clock input for ICSP and ICD
operation.
Remappable peripheral pin 9 input.
Remappable peripheral pin 9 output.
LATB<7> data output.
PORTB<7> data input; weak pull-up when RBPU bit is
cleared.
Interrupt-on-change pin.
Serial execution data output for ICSP and ICD operation.
Serial execution data input for ICSP and ICD operation.
Remappable peripheral pin 10 input.
Remappable peripheral pin 10 output.
2
2
2
2
C™ clock input (MSSP1 module).
C clock output (MSSP1 module).
C data input (MSSP1 module).
C/SMBus.
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Description
© 2009 Microchip Technology Inc.
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