PIC18F46J50-I/PT Microchip Technology, PIC18F46J50-I/PT Datasheet - Page 165

• Manufacturer Part Number: PIC18F46J50-I/PT
• Description: IC PIC MCU FLASH 64KB 44-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46J50-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 22
• Ram Memory Size: 3.6875KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• No. Of Pwm Channels: 2
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Interface Type: I2C/SPI/USART/USB
• On-chip Adc: 13-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164330 - MODULE SKT FOR 44TQFP 18F45J10
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REGISTER 10-2:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0
CSF1
2:
This register is only available in 44-pin devices.
These bits have no effect when their corresponding pins are used as address lines.
CSF<1:0>: Chip Select Function bits
11 = Reserved
10 = Chip select function is enabled and PMCS acts as chip select (in Master mode). Up to
01 = Reserved
00 = Chip select function is disabled (in Master mode). All 16 address bits can be generated.
ALP: Address Latch Polarity bit
1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL and PMALH)
Unimplemented: Maintain as ‘0’
CS1P: Chip Select Polarity bit
1 = Active-high (PMCS)
0 = Active-low (PMCS)
BEP: Byte Enable Polarity bit
1 = Byte enable active-high (PMBE)
0 = Byte enable active-low (PMBE)
WRSP: Write Strobe Polarity bit
For Slave modes and Master Mode 2 (PMMODEH<1:0> = 00,01,10):
1 = Write strobe active-high (PMWR)
0 = Write strobe active-low (PMWR)
For Master Mode 1 (PMMODEH<1:0> = 11):
1 = Enable strobe active-high (PMENB)
0 = Enable strobe active-low (PMENB)
RDSP: Read Strobe Polarity bit
For Slave modes and Master Mode 2 (PMMODEH<1:0> = 00,01,10):
1 = Read strobe active-high (PMRD)
0 = Read strobe active-low (PMRD)
For Master Mode 1 (PMMODEH<1:0> = 11):
1 = Read/write strobe active-high (PMRD/PMWR)
0 = Read/write strobe active-low (PMRD/PMWR)
R/W-0
CSF0
13 address bits only can be generated.
PMCONL: PARALLEL PORT CONTROL REGISTER LOW BYTE (BANKED F5Eh)
W = Writable bit
‘1’ = Bit is set
R/W-0
ALP
(2)
(2)
(2)
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F46J50 FAMILY
R/W-0
CS1P
(2)
R/W-0
BEP
x = Bit is unknown
WRSP
R/W-0
DS39931C-page 165
R/W-0
RDSP
bit 0
(1)