PIC18F46J50-I/PT Microchip Technology, PIC18F46J50-I/PT Datasheet - Page 348

• Manufacturer Part Number: PIC18F46J50-I/PT
• Description: IC PIC MCU FLASH 64KB 44-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46J50-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 22
• Ram Memory Size: 3.6875KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• No. Of Pwm Channels: 2
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Interface Type: I2C/SPI/USART/USB
• On-chip Adc: 13-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164330 - MODULE SKT FOR 44TQFP 18F45J10
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F46J50 FAMILY
20.5
Figure 20-3 displays the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT<2:0> bits are cleared. A conversion is started
after the following instruction to allow entry into Sleep
mode before the conversion begins.
Figure 20-4 displays the operation of the A/D Converter
after the GO/DONE bit has been set, the ACQT<2:0>
bits are set to ‘010’ and selecting a 4 T
time before the conversion starts.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2 T
started. After this wait, acquisition on the selected
channel is automatically started.
FIGURE 20-3:
FIGURE 20-4:
DS39931C-page 348
Note:
(Holding capacitor continues
acquiring input)
AD
Set GO/DONE bit
wait is required before the next acquisition can be
1
conversion
A/D Conversions
T
T
Set GO/DONE bit
CY
Automatic
Acquisition
Time
ACQT
Holding capacitor is disconnected from analog input (typically 100 ns)
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
2
- T
AD
Cycles
Conversion starts
T
3
AD
sample.
A/D CONVERSION T
A/D CONVERSION T
1 T
4
AD
b9
2 T
Conversion starts
(Holding capacitor is disconnected)
1
This
AD
b8
3 T
b9
2
AD
AD
means
Next Q4: ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
b7
Next Q4: ADRESH/ADRESL are loaded, GO/DONE bit is cleared,
4 T
acquisition
b8
3
AD
AD
AD
b6
5 T
CYCLES (ACQT<2:0> = 000, T
CYCLES (ACQT<2:0> = 010, T
ADIF bit is set, holding capacitor is reconnected to analog input.
the
ADIF bit is set, holding capacitor is connected to analog input.
b7
4
AD
b5
6 T
T
5
b6
AD
AD
b4
7 T
Cycles
20.6
An A/D conversion can be started by the Special Event
Trigger of the ECCP2 module. This requires that the
CCP2M<3:0> bits (CCP2CON<3:0>) be programmed
as ‘1011’ and that the A/D module is enabled (ADON
bit is set). When the trigger occurs, the GO/DONE bit
will be set, starting the A/D acquisition and conversion,
and the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
(moving ADRESH/ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition period is either timed by
the user, or an appropriate T
the Special Event Trigger sets the GO/DONE bit (starts
a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
b5
6
AD
b3
8
Use of the ECCP2 Trigger
b4
T
7
AD
b2
9 T
b3
8
AD
b1
10
ACQ
ACQ
T
b2
9
AD
© 2009 Microchip Technology Inc.
b0
11
= 0)
= 4 T
ACQ
10
b1
time is selected before
AD
b0
)
11