PIC18F46J50-I/PT Microchip Technology, PIC18F46J50-I/PT Datasheet - Page 153

• Manufacturer Part Number: PIC18F46J50-I/PT
• Description: IC PIC MCU FLASH 64KB 44-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46J50-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 22
• Ram Memory Size: 3.6875KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• No. Of Pwm Channels: 2
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Interface Type: I2C/SPI/USART/USB
• On-chip Adc: 13-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164330 - MODULE SKT FOR 44TQFP 18F45J10
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REGISTER 9-18:
REGISTER 9-19:
REGISTER 9-20:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
bit 4-0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
bit 4-0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
bit 4-0
U-0
U-0
U-0
—
—
—
Unimplemented: Read as ‘0’
SCK2R<4:0>: Assign SPI2 Data Input (SDI2) to the Corresponding RPn Pin bits
Unimplemented: Read as ‘0’
SS2R<4:0>: Assign SPI2 Slave Select Input (SS2IN) to the Corresponding RPn Pin bits
Unimplemented: Read as ‘0’
OCFAR<4:0>: Assign PWM Fault Input (FLT0) to the Corresponding RPn Pin bits
U-0
U-0
U-0
—
—
—
RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 (BANKED EFCh)
RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23 (BANKED EFDh)
RPINR24: PERIPHERAL PIN SELECT INPUT REGISTER 24 (BANKED EFEh)
R/W = Readable, Writable if IOLOCK = 0
W = Writable bit
‘1’ = Bit is set
R/W = Readable, Writable if IOLOCK = 0
W = Writable bit
‘1’ = Bit is set
R/W = Readable, Writable if IOLOCK = 0
W = Writable bit
‘1’ = Bit is set
U-0
U-0
U-0
—
—
—
OCFAR4
SCK2R4
SS2R4
R/W-1
R/W-1
R/W-0
U = Unimplemented bit, read as ‘0’
U = Unimplemented bit, read as ‘0’
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
‘0’ = Bit is cleared
‘0’ = Bit is cleared
PIC18F46J50 FAMILY
OCFAR3
SCK2R3
SS2R3
R/W-1
R/W-1
R/W-0
OCFAR2
SCK2R2
SS2R2
R/W-1
R/W-1
R/W-0
x = Bit is unknown
x = Bit is unknown
x = Bit is unknown
OCFAR1
SCK2R1
SS2R1
R/W-1
R/W-1
R/W-0
DS39931C-page 153
OCFAR0
SCK2R0
SS2R0
R/W-1
R/W-1
R/W-0
bit 0
bit 0
bit 0