PIC18F46J50-I/PT Microchip Technology, PIC18F46J50-I/PT Datasheet - Page 138

• Manufacturer Part Number: PIC18F46J50-I/PT
• Description: IC PIC MCU FLASH 64KB 44-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46J50-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 22
• Ram Memory Size: 3.6875KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• No. Of Pwm Channels: 2
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Interface Type: I2C/SPI/USART/USB
• On-chip Adc: 13-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164330 - MODULE SKT FOR 44TQFP 18F45J10
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F46J50 FAMILY
TABLE 9-7:
TABLE 9-8:
DS39931C-page 138
RC6/PMA5/
TX1/CK1/RP17
RC7/RX1/DT1/
SDO1/RP18
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
Note 1:
PORTC
LATC
TRISC
Name
Pin
2:
input/output; I
is overridden for this option)
Enhanced PWM output is available only on PIC18F4XJ50 devices.
This bit is only available on 44-pin devices.
TRISC7
LATC7
PORTC I/O SUMMARY
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7
RC7
Function
PMA5
SDO1
RP17
RP18
RC6
CK1
RC7
RX1
TX1
DT1
2
(2)
C/SMB = I
TRISC6
LATC6
Bit 6
RC6
Setting
TRIS
1
0
1
0
0
1
0
1
0
1
0
1
1
0
0
1
0
2
C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or
TRISC5
LATC5
Bit 5
RC5
I/O
O
O
O
O
O
O
O
O
O
1
I
I
I
I
I
I
I
(1)
(CONTINUED)
ST/TTL Parallel Master Port io_addr_in<5>.
Type
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
TRISC4
I/O
ST
ST
ST
ST
ST
ST
ST
LATC4
Bit 4
RC4
PORTC<6> data input.
LATC<6> data output.
Parallel Master Port address.
Asynchronous serial transmit data output (EUSART
module); takes priority over port data. User must configure
as output.
Synchronous serial clock input (EUSART module).
Synchronous serial clock output (EUSART module); takes
priority over port data.
Remappable peripheral pin 17 input.
Remappable peripheral pin 17 output.
PORTC<7> data input.
LATC<7> data output.
Asynchronous serial receive data input (EUSART module).
Synchronous serial data input (EUSART module). User
must configure as an input.
Synchronous serial data output (EUSART module); takes
priority over port data.
SPI data output (MSSP1 module).
Remappable peripheral pin 18 input.
Remappable peripheral pin 18 output.
Bit 3
—
—
—
TRISC2
LATC2
Bit 2
RC2
Description
TRISC1
LATC1
Bit 1
RC1
© 2009 Microchip Technology Inc.
TRISC0
LATC0
Bit 0
RC0
on page:
Values
Reset
86
86
86