MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 108
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MCF5253VM140J
Manufacturer Part Number
MCF5253VM140J
Description
IC MCU 2.1MIPS 140MHZ 225MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF525xr
Datasheets
1.MCF5253VM140J.pdf
(34 pages)
2.MCF5253VM140J.pdf
(8 pages)
3.MCF5253VM140J.pdf
(648 pages)
4.MCF5253VM140J.pdf
(2 pages)
Specifications of MCF5253VM140J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
140MHz
Connectivity
CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
Peripherals
DMA, WDT
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 70°C
Package / Case
225-MAPBGA
Processor Series
MCF525x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5253VM140J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Synchronous DRAM Controller Module
7.3.1
The DRAM controller registers memory map is shown in
7.3.1.1
The DRAM control register (DCR),
7-4
Address MBAR + 0x100
MBAR
Offset
0x10C
0x100
0x104
0x108
0x110
0x114
.
Field
NAM
COC
Reset
SO
15
14
13
12
W
R
Synchronous operation. Selects synchronous or asynchronous mode. When in synchronous mode, the DRAM
controller can be switched to ADRAM mode only by resetting the MCF5253.
0 Asynchronous DRAM. Default at reset. Do not use.
1 Synchronous DRAM
Note: bit setting SO = 0 is a legacy mode. Do not use. First action must always be to set this bit.
Reserved, should be cleared.
No address multiplexing. Some implementations require external multiplexing. For example, when linear addressing
is required, the DRAM should not multiplex addresses on DRAM accesses.
0 The DRAM controller multiplexes the external address bus to provide column addresses.
1 The DRAM controller does not multiplex the external address bus to provide column addresses.
Command on SDRAM clock enable (BCLKE). Implementations that use external multiplexing (NAM = 1) must
support command information to be multiplexed onto the SDRAM address bus.
0 BCLKE functions as a clock enable; self-refresh is initiated by the DRAM controller through DCR[IS].
1 BCLKE drives command information. Because BCLKE is not a clock enable, self-refresh cannot be used (setting
DCR[IS]). Thus, external logic must be used if this functionality is desired. External multiplexing is also responsible
for putting the command information on the proper address bit.
SO
15
0
DRAM control register (DCR)
DRAM address and control register 0 (DACR0) [See
DRAM Controller Registers
Table 7-4. DRAM Control Register (DCR) Field Descriptions (Synchronous Mode)
DRAM mask register block 0 (DMR0) [See
DRAM Control Register (DCR) (Synchronous Mode)
14
–
[31:24]
Figure 7-3. DRAM Control Register (DCR) (Synchronous Mode)
NAM
13
–
COC
12
–
Table 7-3. DRAM Controller Registers
[Section 7.3.1, “DRAM Controller
Figure
IS
11
MCF5253 Reference Manual, Rev. 1
–
10
–
7-3, controls refresh logic.
RTIM
(Synchronous
Section 7.3.1.3, “DRAM Controller Mask Registers
–
9
Description
Reserved
Reserved
Reserved
–
Section 7.3.1.2, “DRAM Address and Control (DACR0)
8
[23:16]
Table
Mode)”]
–
7
Registers”]
7-3.
–
6
5
–
RC
–
4
[15:8]
Freescale Semiconductor
–
3
Access: User read/write
Reserved
2
–
(DMR0)”]
[7:0]
–
1
–
0
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