MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 16
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MCF5253VM140J
Manufacturer Part Number
MCF5253VM140J
Description
IC MCU 2.1MIPS 140MHZ 225MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF525xr
Datasheets
1.MCF5253VM140J.pdf
(34 pages)
2.MCF5253VM140J.pdf
(8 pages)
3.MCF5253VM140J.pdf
(648 pages)
4.MCF5253VM140J.pdf
(2 pages)
Specifications of MCF5253VM140J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
140MHz
Connectivity
CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
Peripherals
DMA, WDT
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 70°C
Package / Case
225-MAPBGA
Processor Series
MCF525x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5253VM140J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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19.2.5.4
19.3
Chapter 20
Background Debug Mode (BDM) Interface
20.1
20.1.1
20.1.2
20.1.3
20.1.4
20.1.5
20.1.6
20.1.7
20.2
20.2.1
20.2.1.1
20.2.1.2
20.2.1.3
20.2.1.4
20.2.1.5
20.2.1.6
20.2.1.7
20.2.1.8
20.2.1.9
20.2.1.10
20.2.1.11
20.3
20.3.1
20.3.2
20.3.2.1
20.3.2.2
20.3.3
20.3.3.1
20.3.4
20.3.4.1
20.3.4.1.1
20.3.4.1.2
20.3.4.1.3
20.3.4.1.4
20.3.4.1.5
20.3.4.1.6
20.3.4.1.7
20.3.4.1.8
20.3.4.1.9
xvi
Creating Appropriate Boot Record Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7
Debug Support Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
Real-Time Trace Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3
Background-Debug Mode (BDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6
Breakpoint (BKPT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2
Debug Data (DDATA[3:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2
Development Serial Clock (DSCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2
Development Serial Input (DSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2
Development Serial Output (DSO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2
Processor Status (PST[3:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2
Processor Status Clock (PSTCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3
Processor Status Signal Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4
CPU Halt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7
BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8
BDM Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10
Command Sequence Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12
Boot from IDE Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6
Continue Execution (PST = $0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4
Begin Execution of an Instruction (PST = $1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4
Entry into User Mode (PST = $3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4
Begin Execution of PULSE or WDDATA instructions (PST = $4). . . . . . . . . . . . . . . 20-4
Begin Execution of Taken Branch (PST = $5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5
Begin Execution of RTE Instruction (PST = $7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6
Begin Data Transfer (PST = $8–$B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6
Exception Processing (PST = $C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6
Emulator Mode Exception Processing (PST = $D) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6
Processor Stopped (PST = $E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6
Processor Halted (PST = $F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6
Receive Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9
Transmit Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9
BDM Command Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10
Command Set Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-13
No Operation (NOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-21
Read Address/Data Register (RAREG/RDREG) . . . . . . . . . . . . . . . . . . . . . . . . . 20-13
Write Address/Data Register (WAREG and WDREG) . . . . . . . . . . . . . . . . . . . . 20-14
Read Memory Location (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-14
Write Memory Location (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-16
Dump Memory Block (DUMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-17
Fill Memory Block (FILL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-19
Resume Execution (GO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-21
Read Control Register (RCREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor
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