MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 301

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

17.1.2
The discussion in this section accompanies
diagram.
There are four serial audio interface blocks (5–11) labeled as follows:
As shown in
(19). The receiver is capable of taking its input signal from four possible EBU inputs:
There is one IEC958 transmitter with two outputs (30), one carries the “consumer” C-channel, the other
the “professional” C-channel.
Four audio interface receivers (IIS1, IIS3, and the two EBU receivers) send their received data on an
internal 40-bit wide bus, the Internal Audio Data Bus. Every transmitter sources its data to be transmitted
from this same internal bus. Every transmitter has a multiplexer to select the data source. Possible sources
are (IIS1 receiver, IIS3 receiver, two EBU receivers, processor data output1, processor data output2,
processor data output 3). Every transmitter also has a FIFO after the multiplexer. This FIFO gives the data
source some freedom when data is generated. The FIFOs compensate for phase shifts when a transmitter
takes data from another receiver. In the case that the transmitter sends out processor-generated data, the
FIFO allows the processor to send several audio words in one burst to the audio transmitter.
To allow the processor to receive and transmit audio data, an interface is present between the internal
Audio Data Bus and the ColdFire memory space. As shown in
memory map as Processor Data Interface Registers. Three of these are Processor Data Out registers,
PDOR1, PDOR2 and PDOR3. When the processor writes to one of these registers, the data is sent directly
to the Internal Audio Data Bus, and depending on the setting of the multiplexers (13, 15, and 24) it will
end up in one or several of the transmit FIFOs (12, 14, and 25). There are three Processor Data In registers,
PDIR1, PDIR2, and PDIR3. When the processor reads from one of these address locations, it actually
reads data from one of the FIFOs (17, 17a, or 17b). These FIFOs receive data from the Internal Audio
Data Bus using multiplexers (16, 16a, and 16b). Depending on the setting of the multiplexers, data from
one of the audio data receivers will end in the FIFOs. Possible receivers for the three PDIR channels are
IIS1 receiver, IIS3 receiver and the two IEC958 receivers.
Besides the mechanism to let the processor access the audio data, there are several interrupts and control
registers to allow the processor to determine when it should read or write data to the appropriate Processor
Data Interface Register.
Freescale Semiconductor
1. IIS1: Capable of transmitting and receiving audio data.
2. IIS2: Transmit only.
3. IIS3: Receive only.
4. IIS4: Only SCLK4 input / output is available. This is intended to be used with the ADC circuit
1. EBUIN1
2. EBUIN2
3. EBUIN3
4. EBUIN4
under certain conditions see
Audio Interface Structure
Figure
17-1, there two IEC958 receivers. The source selector (18) and the receiver block itself
Chapter 12, “Analog to Digital Converter
MCF5253 Reference Manual, Rev. 1
Figure 17-1
by identifying the blocks called out (in bold) in the
Figure
17-1, this interface is seen in the
(ADC)”
Audio Interface Module (AIM)
for details.
17-3