MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 54

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Signal Description
2.9
The following signals transfer serial data between the three UART modules and external peripherals.
2.10
The following signal provides an external interface to Timer0. One 16-bit timers can trigger external
events or both 16-bit timers can trigger internal interrupts.
2.11
The following signals provide the external audio interface.
2-8
I
Serial Module Signal
2
I
c Module Signal
I
2
2
Request To Send
C Serial Clock
C Serial Data
Clear To Send
Transmit Data
Receive Data
Timer Signal
Timer Output
Serial Module Signals
Timer Module Signals
Serial Audio Interface Signals
The SCL0/SDATA1_BS1/GPIO41, and SCL1/TXD1/GPIO10 bidirectional signals are the clock signal for
first and second I
all I
Signals are multiplexed.
The SDA0/SDATA3/GPIO42 and SDA1/RXD1/GPIO44 bidirectional signals are the data input/output for
the first and second serial I
Signals are multiplexed.
The RXD0/GPIO46, SDA1/RXD1/GPIO44, and EF/RXD2/GPIO6 are the inputs on which serial data is
The UART transmits serial data on the TXD0/GPIO45, SCL1/TXD1/GPIO10, and XTRIM/TXD2/GPIO0
received by the UART. Data is sampled on RxD[2:0] on the rising edge of the serial clock source, with
the least significant bit received first.
output signals. Data is transmitted on the falling edge of the serial clock source, with the least significant
bit transmitted (LSB) first. When no data is being transmitted or the transmitter is disabled, these two
signals are held high. TxD[2:0] are also held high in local loopback mode.
The DDATA3/RTS0/GPOI4 and DDATA1/RTS1/SDATA2_BS2/GPIO2 request-to-send outputs indicate
to the peripheral device that UART0/1 are ready to send data and requires a clear-to-send signal to
initiate transfer. The third UART lacks flow control using RTS/CTS.
Peripherals drive the DDATA2/CTS0/GPIO3 and DDATA0/CTS1/SDATA0_SDIO1/GPIO1 inputs to
indicate to the MCF5253 serial module that it can begin data transmission. The third UART lacks flow
control using RTS/CTS.
2
The SDATAO1/TOUT0/GPIO18 programmable output pulse or toggle on various timer events.
C devices drive this signal to synchronize I
2
C module operation. The I
Table 2-4. Serial Module Signals
Table 2-5. Timer Module Signals
MCF5253 Reference Manual, Rev. 1
Table 2-3. I
2
C interface.
2
C Module Signals
2
C module controls this signal when the bus is in master mode;
Description
2
Description
Description
C timing.
Freescale Semiconductor