MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 83
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MCF5253VM140J
Manufacturer Part Number
MCF5253VM140J
Description
IC MCU 2.1MIPS 140MHZ 225MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF525xr
Datasheets
1.MCF5253VM140J.pdf
(34 pages)
2.MCF5253VM140J.pdf
(8 pages)
3.MCF5253VM140J.pdf
(648 pages)
4.MCF5253VM140J.pdf
(2 pages)
Specifications of MCF5253VM140J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
140MHz
Connectivity
CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
Peripherals
DMA, WDT
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 70°C
Package / Case
225-MAPBGA
Processor Series
MCF525x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5253VM140J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Freescale Semiconductor
Offset: MBAR2BAS + 0 x 180
PLLPWRDWN
Reset
Reset
AUDIOSEL
VCXOOUT
VCXODIV
CPUDIV
PLLDIV
CRSEL
SLEEP
CLSEL
W
W
LOCK
30–28
26–24
21–20
19–12
R LOCK
R
Field
8–4
3–2
31
27
23
22
11
10
9
31
15
0
0
VCXODIV[3:0]
Read-only bit. Set if PLL is locked
CPU clock divider
0 Fin = CRIN
1 Fin = CRIN/2
If (pull-up on address pin A20/A24):
If (pull-down on address pin A20/A24 && AUDIOSEL = 1):
If (pull-down on address pin A20/A24 && AUDIOSEL = 0):
PLL compare frequency is VCXO frequency divided by (VCXODIV)
0 Switch back to operational mode
1 Switch device to Sleep mode, including stopping clocks
0 PLL normal operation
1 Disable PLL to power-down mode
Input frequency (Fin) is divided by (PllDiv) to determine the PLL compare frequency.
VCXO output divider
MCLK1 and MCLK2 select
Reserved.
Reserved, should be cleared.
Reserved, should be cleared.
30
14
0
0
Faudio = LRCK3/AUDIOCLK/GPIO43
Faudio = CRIN
Faudio = CRIN/2
CLSEL
29
13
0
0
28
12
0
0
SLEEP
Table 4-2. PLLCONFIG Field Descriptions
27
11
0
0
Figure 4-2. PLLCONFIG Register
MCF5253 Reference Manual, Rev. 1
26
10
0
0
CPUDIV
POWER
DOWN
PLL
25
0
0
9
Description
24
0
0
8
CRSEL
23
0
7
0
PLLDIV
AUDIO
SEL
22
0
0
6
21
0
5
0
Phase-Locked Loop and Clock Dividers
20
0
0
4
VCXOOUT
19
0
0
3
Access: User read/write
VCXODIV[7:4]
18
0
0
2
17
0
0
1
Notes
4, 12
5, 10
8, 9
11
2
7
–
3
–
–
–
5
6
4-3
BYP
PLL
16
0
0
0
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