MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 444
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MCF5253VM140J
Manufacturer Part Number
MCF5253VM140J
Description
IC MCU 2.1MIPS 140MHZ 225MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF525xr
Datasheets
1.MCF5253VM140J.pdf
(34 pages)
2.MCF5253VM140J.pdf
(8 pages)
3.MCF5253VM140J.pdf
(648 pages)
4.MCF5253VM140J.pdf
(2 pages)
Specifications of MCF5253VM140J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
140MHz
Connectivity
CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
Peripherals
DMA, WDT
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 70°C
Package / Case
225-MAPBGA
Processor Series
MCF525x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5253VM140J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Advanced Technology Attachment Controller (ATA)
23.5.2
This section contains the detailed register descriptions for the ATA registers.
23.5.2.1
The ATA interface works both in little endian or big endian mode. The addresses of all registers are
independent of endianess mode. (they remain same.) The few 16-bit and 32-bit registers represent strings
of 2 or 4 bytes. The byte order in the 16-bit or 32-bit register is dependent on endianess selection.
23-18
MBAR2 + 0x81C
(FIFO_DATA_16)
(FIFO_DATA_32)
MBAR2 + 0x818
Name
Name
Register Descriptions
Endianness
Address
Address
Address
Address
Address
Address
Address
Name
Name
W
W
W
R
R
R
15
31
15
14
30
14
Table 23-9. ATA Register Summary (continued)
29
13
13
W
W
W
W
W
W
W
R
R
R
R
R
R
R
MCF5253 Reference Manual, Rev. 1
28
12
12
fifo_rst_
intrq1
intrq1
ata_
ata_
b
7
7
27
11
11
ata_rst_
underflo
under-
under-
26
10
10
fifo_
fifo_
fifo_
flow
flow
w
b
6
6
25
9
9
fifo_data[23:16]
fifo_data[15:0]
fifo_data[15:0]
fifo_tx_
overflo
over-
over-
fifo_
fifo_
fifo_
flow
flow
en
24
w
5
5
TIME_CYC[7:0]fifo_data[15:0]
8
8
23
FIFO_ALARM[7:0]
7
7
fifo_rcv
controll
controll
FIFO_FILL[7:0]
_en
idle
idle
er_
er_
4
4
22
6
6
pending
dma_
irtrq2
irtrq2
21
ata_
ata_
5
5
3
3
20
4
4
dma_ult
ra_se-
lected
Freescale Semiconductor
2
2
19
3
3
18
2
2
dma_
write
1
1
17
1
1
iordy_
en
16
0
0
0
0
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