MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 396

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Background Debug Mode (BDM) Interface
be disabled during the read/write process so the exact bit-wise eMAC register contents are accessed. For
example, a BDM read of an accumulator (ACCx) requires the following sequence:
Bdm Read ACCx (
Likewise to write an accumulator register, the following BDM sequence is needed:
Bdm Write ACCx (
Additionally, writes to the accumulator extension registers must be performed after the corresponding
accumulators are updated because a write to any accumulator alters the corresponding extension register
contents.
Command Sequence:
Operand Data:
The single operand is the 32-bit Rc control register select field.
Result Data:
The contents of the selected control register are returned as a longword value. The data is returned most
significant word first. For those control registers with widths less than 32 bits, only the implemented
portion of the register is guaranteed to be correct. The remaining bits of the longword are undefined.
20.4
The ColdFire Family provides support for the debug of real-time applications. For these types of
embedded systems, the processor cannot be halted during debug, but must continue to operate. The
foundation of this area of debug support is that while the processor cannot be halted to allow debugging,
the system can generally tolerate small intrusions into the real-time operation.
The debug module provides a number of hardware resources to support various hardware breakpoint
functions. Specifically, three types of breakpoints are supported: PC with mask, operand address range,
and data with mask. These three basic breakpoints can be configured into one- or two-level triggers with
20-26
rcreg macsr; // read current macsr contents & save
wcreg #0,macsr; // disable all rounding modes
rcreg ACCx; // read the desired accumulator
wcreg #saved_data,macsr; // restore the original macsr
rcreg macsr; // read current macsr contents & save
wcreg #0,macsr; // disable all rounding modes
wcreg #data,ACCx; // write the desired accumulator
wcreg #saved_data,macsr; // restore the original macsr
)
RCREG
Real-Time Debug Support
???
“NOT READY”
MS ADDR
Figure 20-27. Read Control Register Command Sequence
MCF5253 Reference Manual, Rev. 1
“NOT READY”
MS ADDR
CONTROL
REGISTER
READ
MS RESULT
“NOT READY”
BERR
XXX
XXX
XXX
Freescale Semiconductor
“NOT READY”
LS RESULT
NEXT CMD
NEXT CMD