MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 324

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Audio Interface Module (AIM)
17.6.3.1
There is a synchronization issue on start-up between the MCF5253 and some channel encoders. On
start-up, the RCK clock is kept silent. At a certain point in time, the CDR60
and then it will require that the first symbol transmitted from the MCF5253 to the CDR60 is a sync symbol.
If this is not the case, the CDR60 fails to synchronize.
To solve the synchronization issue, the counter that determines the sync position can be preset using the
register CdTextControl
17.6.3.2
When RCK is not clocking, it is possible to control the subcode byte number that will be sent out next by
the CD-Subcode interface by writing CdTextControl with PresetEn set to 1.
17.6.4
Source selection of data transmitted into the User Channel of the IEC958 transmitter is selected by bits
(1,0) of register EBUConfig.
17.7
The interface between the processor and the Audio Modules is given in this section.
a simplified picture of the interface between the audio modules and the processor core.
1.
17-26
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When 0 is written to presetCount, the next byte sent out is a CD-Subcode sync byte. (SFSY low).
When a value (97–i) is written to presetCount, i non-sync bytes are transmitted, followed by a sync
byte.
After writing to CdTextControl with PresetEn set to 1, next bit out is always the first bit of a new
byte.
Writing CdTextControl with PresetEn set to 1, while RCK is running, will result in unpredictable,
undefined operation.
When selected the source is the IEC958 receiver, every user channel data byte received into the
input of the IEC958 user channel, is inserted into the outgoing stream at approximately. the same
time it was found in the incoming stream.
When the selected source is CD-Subcode, every data byte transmitted over the CD-Subcode output
is also inserted into the IEC958 output stream. The most significant bit of every byte is transmitted
as a “1”. All sync symbols are transmitted as all-0.
In case the RCK clock is not present, it is still possible to use the CD-Subcode interface to assemble
the outgoing IEC958 User channel data. In this case, bit UChanTxTim in register
CDTEXTCONTROL must be set ‘1’
registers to be controlled by the IEC958 transmitter. One symbol (data or sync) will be transmitted
into the IEC958 output every 12 User Channel data bits.
CDR60 is the informal name for Philips CD-R channel encoder
Processor Interface Overview
Inserting CD User Channel Data Into IEC958 Transmit Data
Free Running Counter Synchronization
Controlling the SFSY Sync Position
(Table
17-11).
MCF5253 Reference Manual, Rev. 1
(Table
17-11). It will cause the timing to the CD-Subcode
1
will start clocking the RCK,
Freescale Semiconductor
Figure
17-15, shows