MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 121
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MCF5253VM140J
Manufacturer Part Number
MCF5253VM140J
Description
IC MCU 2.1MIPS 140MHZ 225MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF525xr
Datasheets
1.MCF5253VM140J.pdf
(34 pages)
2.MCF5253VM140J.pdf
(8 pages)
3.MCF5253VM140J.pdf
(648 pages)
4.MCF5253VM140J.pdf
(2 pages)
Specifications of MCF5253VM140J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
140MHz
Connectivity
CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
Peripherals
DMA, WDT
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 70°C
Package / Case
225-MAPBGA
Processor Series
MCF525x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5253VM140J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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The associated CBM bits should also be initialized. After DACR[IMRS] is set, the next access to the
SDRAM address space generates the
selected to place the correct mode information on the SDRAM address pins. The address is not multiplexed
for the
of that access needs the correct mode programming information on the correct address bits.
Figure 7-12
7.6
This example interfaces a Samsung K4S641633 1M x 16-bit x 4 bank SDRAM component to a MCF5253
operating at 80 MHz (40 MHz bus).
Freescale Semiconductor
MRS
SDRAM Example
command. The
shows the
12 rows, 8 columns
Two bank-select lines to access four internal banks
ACTV
Period between auto refresh and
ACTV
Precharge command to
Last data input to
Auto refresh period for 4096 rows (t
-to-read/write delay (t
command to precharge command (t
MRS
MRS
SDRAS, SDCAS
command, which occurs in the first clock of the bus cycle.
PALL
Figure 7-12. Mode Register Set (
Table 7-12. SDRAM Example Specifications
access can be a read or write. The important thing is that the address output
command (t
SD_CS0
D[31:16]
ACTV
A[31:0]
SDWE
RCD
Parameter
BCLK
Table 7-12
MCF5253 Reference Manual, Rev. 1
MRS
command (t
)
ACTV
command to that SDRAM. The address of the access should be
RWL
REF
command (t
)
)
MRS
lists design specifications for this example.
RAS
RP
)
)
RC
)
MRS
) Command
1 bus clock (25 nS)
Specification
Synchronous DRAM Controller Module
20 nS (min.)
48 nS (min.)
20 nS (min.)
64 mS
70 nS
–
–
7-17
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