MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 17
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MCF5253VM140J
Manufacturer Part Number
MCF5253VM140J
Description
IC MCU 2.1MIPS 140MHZ 225MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF525xr
Datasheets
1.MCF5253VM140J.pdf
(34 pages)
2.MCF5253VM140J.pdf
(8 pages)
3.MCF5253VM140J.pdf
(648 pages)
4.MCF5253VM140J.pdf
(2 pages)
Specifications of MCF5253VM140J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
140MHz
Connectivity
CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
Peripherals
DMA, WDT
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 70°C
Package / Case
225-MAPBGA
Processor Series
MCF525x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5253VM140J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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20.3.4.1.10
20.3.4.1.11
20.3.4.1.12
20.3.4.1.13
20.3.4.2
20.4
20.4.1
20.4.1.1
20.4.1.2
20.4.1.2.1
20.5
20.5.1
20.5.2
20.5.3
20.5.4
20.5.5
20.5.6
20.5.7
20.5.8
20.5.9
Chapter 21
IEEE 1149.1 Test Access Port (JTAG)
21.1
21.2
21.3
21.3.1
21.3.2
21.3.3
21.3.4
21.3.5
21.4
21.5
21.5.1
21.5.1.1
21.5.1.2
21.5.1.3
21.5.1.4
21.5.1.5
21.5.1.6
21.5.2
21.5.3
21.5.4
21.6
Freescale Semiconductor
Real-Time Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-26
Debug Module Memory Map and Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-29
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4
JTAG Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9
JTAG Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2
Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-27
Address Breakpoint Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-30
Address Attribute Trigger Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-31
Program Counter Breakpoint Register (PBR, PBMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-32
Data Breakpoint Registers (DBR, DBMR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-33
Trigger Definition Register (TDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-35
Configuration/Status Register (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-36
BDM Address Attribute Register (BAAR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-39
Concurrent BDM and Processor Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-39
Freescale-Recommended BDM Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-40
Test Clock (TCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3
Test Reset/Development Serial Clock (TRST/DSCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3
Test Mode Select/ Breakpoint (TMS/BKPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3
Test Data Input/Development Serial Input (TDI/DSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4
Test Data Output/Development Serial Output (TDO/DSO). . . . . . . . . . . . . . . . . . . . . . . . 21-4
ID Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8
JTAG Boundary Scan Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9
JTAG Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9
JTAG Instruction Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
BDM Accesses of the eMAC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-25
Emulator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-28
Debug Module Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-29
EXTEST Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
IDCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
SAMPLE/PRELOAD Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7
CLAMP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7
HIGHZ Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7
BYPASS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8
Read Debug Module Register (RDMREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-24
Reuse of Debug Module Hardware (Rev. A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-29
Write Control Register (WCREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-23
Write Debug Module Register (WDMREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-24
Unassigned Opcodes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-25
MCF5253 Reference Manual, Rev. 1
xvii
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