MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 86
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MCF5253VM140J
Manufacturer Part Number
MCF5253VM140J
Description
IC MCU 2.1MIPS 140MHZ 225MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF525xr
Datasheets
1.MCF5253VM140J.pdf
(34 pages)
2.MCF5253VM140J.pdf
(8 pages)
3.MCF5253VM140J.pdf
(648 pages)
4.MCF5253VM140J.pdf
(2 pages)
Specifications of MCF5253VM140J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
140MHz
Connectivity
CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
Peripherals
DMA, WDT
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 70°C
Package / Case
225-MAPBGA
Processor Series
MCF525x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5253VM140J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Phase-Locked Loop and Clock Dividers
4.3
The Glitch-free Clock Rate divider block works on the PDM (Pulse Density Modulation) principal. As it
is a divider, it only reduces the clock rate output from the PLL module. It does this by gating out
(removing) clock pulses to reach the desired clock rate (operating frequency). This implies that clock
pulses after the Clock Rate divider block may not be equi-distant depending on the chosen divider value.
The re-action time of the Clock Rate divider block is in the order of 20nS.
The Clock Rate divider block is controlled by a 32-bit register as shown in
4.4
The audio clocks and output DAC clocks are derived directly from the CRIN pin. Clock settings depend
on CRSEL, CLSEL, and AUDIOSEL bits, as explained in
AUDIO_CLOCK is completely derived from the AUDIOSEL bit, and this clock is independent of the
other select bits. For the DAC clocks (MCLK2 and MCLK1) the relationship between CRSEL and CLSEL
is defined in
4-6
Offset: MBAR2BAS + 0x170
Reset 0
Clock Rate
W
Select
R 0
Field
31–8
7–0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PLLCR[CLSEL]
Dynamic Clock Switching
Audio Clock Generation
0
0
(Bits 30–28)
Table
0
0
Reserved, should be cleared.
Sets the divider to pass-thru mode and no clock rate reduction is applied. At reset, this bit field is set to 0xFF.
Clock Rate Select = round ((Desired Clock Rate / PLL Output Frequency)
000
001
010
Do not make the PLL output frequency any higher than required for the
actual application. The higher the PLL operating frequency then the higher
the power consumption of the PLL block.
0
0
4-7.
0
0
0
0
PllCR CRsel
0
0
(Bit 23)
0
0
1
1
1
0
0
Table 4-6. ClockRate Field Descriptions
0
0
MCF5253 Reference Manual, Rev. 1
Figure 4-3. ClockRate Register
0
0
pllCR Config
Table 4-7. PLLCR Bit Fields
Audiosel
0
0
(Bit 22)
1
1
1
0
0
0
0
NOTE
0
0
AUDIO_CLOCK
0
0
Description
0
0
CRIN
CRIN
CRIN
Table
0
0
0
0
4-7. As the table shows, the
0
0
0
0
MCLK2
CRIN/2
0
0
CRIN
CRIN
×
Table 4-3
0
0
9
255)
0
0
8
1
7
Freescale Semiconductor
1
6
Access: User read/write
Clock rate select
MCLK1
CRIN/2
CRIN/2
CRIN
1
5
1
4
3
1
2
1
1
1
1
0
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