MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 520
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MCF5253VM140J
Manufacturer Part Number
MCF5253VM140J
Description
IC MCU 2.1MIPS 140MHZ 225MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF525xr
Datasheets
1.MCF5253VM140J.pdf
(34 pages)
2.MCF5253VM140J.pdf
(8 pages)
3.MCF5253VM140J.pdf
(648 pages)
4.MCF5253VM140J.pdf
(2 pages)
Specifications of MCF5253VM140J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
140MHz
Connectivity
CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
Peripherals
DMA, WDT
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 70°C
Package / Case
225-MAPBGA
Processor Series
MCF525x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5253VM140J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Universal Serial Bus Interface
24.8.5.3
The third DWord of a queue element transfer descriptor contains most of the information the host
controller requires to execute a USB transaction (the remaining endpoint-addressing information is
specified in the queue head). Note that some of the field descriptions in
defined in the queue head. See
24-58
30–16
14–12
4–1
Bit
Bit
31
15
0
Total Bytes
to Transfer
C_Page
Name
Name
ioc
T
dt
–
Table 24-52. qTD Alternate Next Element Transfer Pointer (DWord 1) (continued)
qTD Token
Data Toggle. This is the data toggle sequence bit. The use of this bit depends on the setting of the Data
Toggle Control bit in the queue head.
Total Bytes to Transfer. This field specifies the total number of bytes to be moved with this transfer
descriptor. This field is decremented by the number of bytes actually moved during the transaction, only
on the successful completion of the transaction. The maximum value the software may store in this field is
5
field is zero when the host controller fetches this transfer descriptor (and the active bit is set), the host
controller executes a zero-length transaction and retires the transfer descriptor. It is not a requirement for
OUT transfers that Total Bytes To Transfer be an even multiple of QH[Maximum Packet Length]. If the
software builds such a transfer descriptor for an OUT transfer, the last transaction will always be less than
QH[Maximum Packet Length]. Although it is possible to create a transfer up to 20K this assumes the page
is 0. When the offset cannot be predetermined, crossing past the 5th page can be guaranteed by limiting
the total bytes to 16K. Therefore, the maximum recommended transfer is 16K(0x4000).
should issue an interrupt at the next interrupt threshold.
Current Page. This field is used as an index into the qTD buffer pointer list. Valid values are in the range
0x0 to 0x4. The host controller is not required to write this field back when the qTD is retired.
Interrupt On Complete. If this bit is set, it specifies that when this qTD is completed, the Host Controller
Reserved. These bits are reserved and their value has no effect on operation.
Terminate. This bit indicates to the Host Controller that there are no more valid entries in the queue.
0 Pointer is valid (points to a valid Transfer Element Descriptor).
1 Pointer is invalid.
×
4K (0x5000). This is the maximum number of bytes 5 page pointers can access. If the value of this
Section 24.8.6, “Queue Head,”
Table 24-53. qTD Token (DWord 2)
MCF5253 Reference Manual, Rev. 1
Description
Description
for more information on these fields.
Table 24-53
Freescale Semiconductor
reference fields
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