MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 584

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Universal Serial Bus Interface
The data structures defined in the section are (from the device controller's perspective) a mix of read-only
and read/ writable fields. The device controller must preserve the read-only fields on all data structure
writes.
The USB_DR core includes DCD software called the USB 2.0 Device API. The Device API provides an
easy to use Application Program Interface for developing device (peripheral) applications. The Device
API incorporates and abstracts for the application developer all of the elements of the program interface.
Device queue heads are arranged in an array in a continuous area of memory pointed to by the
ENDPOINTLISTADDR pointer. The even –numbered device queue heads in the list support receive
endpoints (OUT/SETUP) and the odd-numbered queue heads in the list are used for transmit endpoints
(IN/INTERRUPT). The device controller will index into this array based upon the endpoint number
received from the USB bus. All information necessary to respond to transactions for all primed transfers
is contained in this list so the Device Controller can readily respond to incoming requests without having
to traverse a linked list.
24.10.1 Endpoint Queue Head
The device Endpoint Queue Head (dQH) is where all transfers are managed. The dQH is a 48-byte data
structure, but must be aligned on 64-byte boundaries. During priming of an endpoint, the dTD (device
24-122
ENDPOINTLISTADDR
Up to
32 elements
The software must ensure that no interface data structure reachable by the
Device Controller spans a 4K-page boundary.
The Endpoint Queue Head List must be aligned to a 2k boundary.
Figure 24-60. End Point Queue Head Organization
Endpoint QH 1
Endpoint QH 0
Endpoint QH 0
MCF5253 Reference Manual, Rev. 1
– Out
– In
– Out
NOTE
NOTE
Endpoint Queue Heads
Transfer
Buffer
Pointer
Transfer Buffer Pointer
Transfer Buffer Pointer
Endpoint
Transfer
Descriptor
Transfer
Buffer
Transfer Buffer
Pointer
Freescale Semiconductor
Transfer
Buffer
Transfer
Buffer
Transfer
Buffer