MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 428
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MCF5253VM140J
Manufacturer Part Number
MCF5253VM140J
Description
IC MCU 2.1MIPS 140MHZ 225MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF525xr
Datasheets
1.MCF5253VM140J.pdf
(34 pages)
2.MCF5253VM140J.pdf
(8 pages)
3.MCF5253VM140J.pdf
(648 pages)
4.MCF5253VM140J.pdf
(2 pages)
Specifications of MCF5253VM140J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
140MHz
Connectivity
CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
Peripherals
DMA, WDT
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 70°C
Package / Case
225-MAPBGA
Processor Series
MCF525x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5253VM140J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Advanced Technology Attachment Controller (ATA)
23.3
The ATA block is a AT attachment host interface. Its main use is to interface with IDE hard disc drives and
ATAPI optical disc drives. It interfaces with the ATA device over a number of ATA signals.
The ATA interface is compliant to the ATA-6 standard and supports the following protocols:
The ATA interface has 2 busses connected:
All internal registers are visible from both busses, allowing smart DMA access to program the interface.
Before accessing the ATA bus, the host must program the timing parameters to be used on the ATA bus.
The timing parameters control the timing on the ATA bus. Most timing parameters are programmable as a
number of clock cycles (1 to 255). Some are implied.
After programming the timing parameters, there are two protocols that can be active at the same time on
the ATA bus:
23-2
•
•
•
•
•
•
PIO mode 0, 1, 2, 3, and 4
multiword DMA mode 0, 1, and 2
Ultra DMA modes 0, 1, 2, 3, and 4 with bus clock of 50 MHz or higher
One CPU bus for communication with the host processor
One DMA bus for communication with the host DMA unit
First protocol. This protocol is a PIO mode access that can be performed at any time by the host
CPU or the host smart DMA to the ATA bus. During PIO mode access, the incoming IP bus cycle
is translated to an ATA bus cycle by the ATA protocol engine. The IP bus cycle is stalled until
completion of the ATA bus cycle on read, or until putting the write data on the ATA bus on write.
Overview
DMA
Bus
CPU
Bus
Bus
Interface
Figure 23-1. ATA Interface Block Diagram
MCF5253 Reference Manual, Rev. 1
Interrupt
Interface
Timing
Parameters
Control
Register
FIFO
control
FIFO
128 bytes
ATA
Protocol
Engine
ATA_RST
ATA_DMARQ
ATA_DMACK
ATA_INTRQ
ATA_IORDY
ATA_D[15:0]
ATA_DIOR
ATA_DIOw
ATA_CS1
ATA_CS0
ATA_A2
ATA_A1
ATA_A0
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