MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 632

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

FlexCAN Module
25.5.7
IMASK n contains one interrupt mask bit per buffer. It enables the CPU to determine which buffer will
generate an interrupt after a successful transmission/reception (that is, when the corresponding IFLAG n
bit is set).
25.5.8
IFLAG n contains one interrupt flag bit per buffer. Each successful transmission/reception sets the
corresponding IFLAG n bit and, if the corresponding IMASK n bit is set, will generate an interrupt.
The interrupt flag is cleared by writing a 1, while writing 0 has no effect.
25-16
BOFFINT
ERRINT
BUFnM
Field
Field
31–0
Offset MBAR2 0x1028 (IMASK0)
Reset 0
2
1
0
W
R
Table 25-8. FlexCAN Error and Status (ERRSTATn) Register Field Descriptions (continued)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bus off interrupt. Used to request an interrupt when the FlexCAN enters the bus off state. The user must write a 1
to clear this bit. Writing 0 has no effect.
0 No bus off interrupt requested.
1 This bit is set when the FlexCAN state changes to bus off. If the CANCTRLn[BOFFMSK] bit is set an interrupt
Error interrupt. Indicates that at least one of the ERRSTATn[15:10] bits is set. The user must write a 1 to clear this
bit. Writing 0 has no effect.
0 No error interrupt request.
1 At least one of the error bits is set. If the CANCTRLn[ERRMSK] bit is set, an interrupt request is generated.
Reserved, should be cleared.
Buffer interrupt mask. Enables the respective FlexCAN message buffer (MB0 to MB31) interrupt. These bits allow
the CPU to designate which buffers will generate interrupts after successful transmission/reception.
0 The interrupt for the corresponding buffer is disabled.
1 The interrupt for the corresponding buffer is enabled.
Note: Setting or clearing an IMASKn bit can assert or negate an interrupt request, if the corresponding IFLAGn bit
Interrupt Mask Register (IMASKn)
Interrupt Flag Register (IFLAGn)
0 0
request is generated. This interrupt is not requested after reset.
it is set.
Table 25-9. FlexCAN Interrupt Mask (IMASKn) Register Field Descriptions
0 0
Figure 25-10. FlexCAN Interrupt Mask (IMASKn) Register
0 0 0
0 0
MCF5253 Reference Manual, Rev. 1
0 0
0 0 0
BUFnM, n=31–0
Description
Description
0 0
0 0
0 0 0
0 0
9
8
0 0
7
Freescale Semiconductor
Access: User read/write
6
0 0 0
5
4
3
0 0
2
1
0
0