MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 485
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MCF5253VM140J
Manufacturer Part Number
MCF5253VM140J
Description
IC MCU 2.1MIPS 140MHZ 225MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF525xr
Datasheets
1.MCF5253VM140J.pdf
(34 pages)
2.MCF5253VM140J.pdf
(8 pages)
3.MCF5253VM140J.pdf
(648 pages)
4.MCF5253VM140J.pdf
(2 pages)
Specifications of MCF5253VM140J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
140MHz
Connectivity
CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
Peripherals
DMA, WDT
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 70°C
Package / Case
225-MAPBGA
Processor Series
MCF525x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5253VM140J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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24.6.3.5
The CTRLDSSEGMENT register is not implemented on the MCF5253.
24.6.3.6
This register contains the beginning address of the Periodic Frame List in the system memory. The host
controller driver loads this register prior to starting the schedule execution by the controller. The memory
structure referenced by this physical memory pointer is assumed to be 4-Kbyte aligned. The contents of
this register are combined with the Frame Index Register (FRINDEX) to enable the controller to step
through the Periodic Frame List in sequence.
Note that this register is shared between the host and device mode functions. In host mode, it is the
PERIODICLISTBASE register; in device mode, it is the DEVICEADDR register. See
“Device Address Register (DEVICEADDR), Non-EHCI,”
Freescale Semiconductor
PERBASE
Address MBAR2 0x754 (Host Mode)
31–12
Reset
Reset
Field
11–0
Table 24-20. Periodic Frame List Base Address (PERIODICLISTBASE) Register Field Descriptions
W
W
R
R
31
15
0
0
Base Address. These bits correspond to memory address signal [31:12]. Used only in host mode.
Reserved.
PERBASE (continued)
Figure 24-18. Periodic Frame List Base Address (PERIODICLISTBASE) Register
Control Data Structure Segment Register (CTRLDSSEGMENT)
Periodic Frame List Base Address Register (PERIODICLISTBASE)
30
14
0
0
USBCMD[FS]
29
13
0
0
100
101
110
111
28
12
0
0
Table 24-19. FRINDEX N Values (continued)
27
11
0
0
MCF5253 Reference Manual, Rev. 1
64 elements (256 bytes)
32 elements (128 bytes)
16 elements (64 bytes)
8 elements (32 bytes)
26
10
0
0
Frame List Size
25
0
0
9
PERBASE
Description
24
0
0
8
23
0
0
7
for more information.
22
0
0
6
FRINDEX N value
21
0
0
5
8
7
6
5
20
0
0
4
Universal Serial Bus Interface
19
0
0
3
Access: User read/write
Section 24.6.3.7,
18
0
0
2
17
0
0
1
24-23
16
0
0
0
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