MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 136

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

1
2
Bus Operation
8.5.3
The Write cycle as shown in
Register (CSR) is programmed to value “0000”. The CS low time is increased with n clocks if n is
programmed into the WS field.
During a write cycle, the MCF5253 sends data to the memory or to a peripheral device.
The write cycle flowchart is
8-8
STATE 3
STATE 4
STATE 5
The external device has a maximum of 1.5 BCLK cycles after the start of S4 to three-state the data bus after data is sampled
in S3 during a read cycle. This applies to basic read cycles and the last transfer of a burst.
The MCF5253 would not drive out data for a minimum of two BCLK cycles. However, another slave device may start driving
the bus as soon as its chip select is asserted. Chip select may be asserted at the beginning of S1, so bus drive must stop
before the end of S0. Under these conditions, data contention on the bus would not exist.
Name
State
1. Sample TA Low
2. Tri-State Data on D[31:16]
3. Start Next Cycle
1. Set RW to Write
2. Place Address on A[23:1]
3. Drive Data on D[31:16]
Data is made available by the external device and is sampled on the rising edge of BCLK with TA asserted. If TA
not asserted before the rising edge of BCLK at the end of the first clock cycle, the MCF5253 inserts wait states
(full clock cycles) until TA is asserted. If internal TA is requested (auto-acknowledge enabled in the chip select
control register, CSCR) then TA is generated internally by the chip select module.
During state 4, TA should be negated by the external device or if auto-acknowledge is enabled will be negated
internally by the chip select module.
CS and OE are negated on the falling edge of state 5 (S5). The MCF5253 stops driving the address lines and RW
on the rising edge of BCLK, terminating the read cycle. The external device must have its drive from the bus. The
external device must stop driving the bus.
The rising edge of BCLK may be the start of state 0 for the next access cycle.
Write Cycle
MCF5253
Figure
Figure 8-6.
Table 8-6. Read Cycle States (continued)
8-6., will occur if the wait cycle field (WS) in the Chip Select Control
Figure 8-5. Write Cycle Flowchart
MCF5253 Reference Manual, Rev. 1
Write cycle timing diagram is
Description
1. Decode Address
2. Store Data on D[31:16]
3. CS unit asserts TA (internal termination) or assert TA
externally for 1 BCLK cycle
(external termination).
1,2
External Memory/Device
Figure
8-7.
Freescale Semiconductor