MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 132
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MCF5253VM140J
Manufacturer Part Number
MCF5253VM140J
Description
IC MCU 2.1MIPS 140MHZ 225MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF525xr
Datasheets
1.MCF5253VM140J.pdf
(34 pages)
2.MCF5253VM140J.pdf
(8 pages)
3.MCF5253VM140J.pdf
(648 pages)
4.MCF5253VM140J.pdf
(2 pages)
Specifications of MCF5253VM140J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
140MHz
Connectivity
CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
Peripherals
DMA, WDT
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 70°C
Package / Case
225-MAPBGA
Processor Series
MCF525x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5253VM140J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Bus Operation
8.3.1
Asserting RSTI causes the MCF5253 processor to enter reset exception processing. When RSTI is
recognized, the data bus is tri-stated, and OE, CS0, and CS1 are negated. See
Operation.”
8.3.2
The BCLK output signal is generated by the internal PLL, and is the system bus clock output used as the
bus timing reference by the external devices. BCLK is always half the frequency of the processor clock.
8.4
The external bus operates at the same speed as the bus clock rate, where all bus operations are synchronous
to the rising edge of BCLK, and the bus chip selects are synchronous to the falling edge of the BCLK,
which is shown in
external DRAM.
8.5
Data transfer between the MCF5253 processor and other devices involves the following signals:
8-4
1. Address bus (A[23:1])
2. RW control
BCLK
OUTPUT
SIGNALS
OUTPUT
CONTROL
INPUTS
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Bus Characteristics
Data Transfer Operation
= Required input setup time relative to BCLK edge
= Required input hold time relative to BCLK edge
= Propagation delay of signal relative to BCLK edge
= Output hold time relative to BCLK edge
Reset In
System Bus Clock Output
Figure
Figure 8-1. Signal Relationship to BCLK for Non-DRAM Access
8-1. The bus characteristics may be somewhat different for interfacing with
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MCF5253 Reference Manual, Rev. 1
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Section 8.7, “Reset
Freescale Semiconductor
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