MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 393
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MCF5253VM140J
Manufacturer Part Number
MCF5253VM140J
Description
IC MCU 2.1MIPS 140MHZ 225MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF525xr
Datasheets
1.MCF5253VM140J.pdf
(34 pages)
2.MCF5253VM140J.pdf
(8 pages)
3.MCF5253VM140J.pdf
(648 pages)
4.MCF5253VM140J.pdf
(2 pages)
Specifications of MCF5253VM140J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
140MHz
Connectivity
CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
Peripherals
DMA, WDT
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 70°C
Package / Case
225-MAPBGA
Processor Series
MCF525x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5253VM140J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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20.3.4.1.10 Write Control Register (WCREG)
The operand (longword) data is written to the specified control register. The write alters all 32 register bits.
Command Sequence:
Operand Data:
Two operands are required for this instruction. The first long operand selects the register to which the
operand data is to be written. The second operand is the data.
Result Data:
Successful write operations return a $FFFF. Bus errors on the write cycle are indicated by the assertion of
bit 16 in the status message and by a data pattern of $0001.
Freescale Semiconductor
WCREG
???
Figure 20-22. Write Control Register Command Sequence
“Not Ready”
MS Addr
Figure 20-21. WCREG Command Sequence
$C0F
$C0E
Rc
Table 20-14. Control Register Map
MCF5253 Reference Manual, Rev. 1
“Not Ready”
“Not Ready”
LS Data
Module Base Address Register (MBAR)
Module Base Address Register (MBAR2)
LS Addr
Register Definition
Write
Control
Register
“Not Ready”
MS Data
“Not Ready”
“Cmd Complete”
Background Debug Mode (BDM) Interface
XXX
Next Cmd
BERR
XXX
“Not Ready”
Next Cmd
20-23
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