MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 22
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MCF5253VM140J
Manufacturer Part Number
MCF5253VM140J
Description
IC MCU 2.1MIPS 140MHZ 225MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF525xr
Datasheets
1.MCF5253VM140J.pdf
(34 pages)
2.MCF5253VM140J.pdf
(8 pages)
3.MCF5253VM140J.pdf
(648 pages)
4.MCF5253VM140J.pdf
(2 pages)
Specifications of MCF5253VM140J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
140MHz
Connectivity
CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
Peripherals
DMA, WDT
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 70°C
Package / Case
225-MAPBGA
Processor Series
MCF525x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5253VM140J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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24.9.9
24.9.9.1
24.9.9.2
24.9.9.3
24.9.9.4
24.9.9.5
24.9.10
24.9.10.1
24.9.10.2
24.9.10.3
24.9.11
24.9.12
24.9.12.1
24.9.12.1.1
24.9.12.1.2
24.9.12.2
24.9.12.2.1
24.9.12.2.2
24.9.12.2.3
24.9.12.2.4
24.9.12.2.5
24.9.12.2.6
24.9.12.2.7
24.9.12.2.8
24.9.12.2.9
24.9.12.3
24.9.12.3.1
24.9.12.3.2
24.9.12.3.3
24.9.12.3.4
24.9.12.3.5
24.9.12.3.6
24.9.12.3.7
24.9.13
24.9.14
24.9.14.1
24.9.14.1.1
24.9.14.1.2
24.9.14.1.3
24.9.14.1.4
24.9.14.1.5
24.9.14.2
24.9.14.2.1
24.9.14.2.2
24.9.14.2.3
xxii
Asynchronous Schedule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-79
Managing Control/Bulk/Interrupt Transfers via Queue Heads. . . . . . . . . . . . . . . . . . . . . 24-84
Ping Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-88
Split Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-89
Port Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-116
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-117
Adding Queue Heads to Asynchronous Schedule . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-80
Removing Queue Heads from Asynchronous Schedule. . . . . . . . . . . . . . . . . . . . . . . 24-81
Empty Asynchronous Schedule Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-83
Asynchronous Schedule Traversal: Start Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-84
Reclamation Status Bit (USBSTS Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-84
Buffer Pointer List Use for Data Streaming with qTDs . . . . . . . . . . . . . . . . . . . . . . . 24-85
Adding Interrupt Queue Heads to the Periodic Schedule . . . . . . . . . . . . . . . . . . . . . . 24-87
Managing Transfer Complete Interrupts from Queue Heads . . . . . . . . . . . . . . . . . . . 24-87
Split Transactions for Asynchronous Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-89
Split Transaction Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-91
Split Transaction Isochronous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-103
Transfer/Transaction Based Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-118
Host Controller Event Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-120
Asynchronous—Do-Complete-Split. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-90
Software Operational Model for FSTNs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-96
Tracking Split Transaction Progress for Isochronous Transfers . . . . . . . . . . . . 24-107
Asynchronous—Do-Start-Split. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-90
Split Transaction Scheduling Mechanisms for Interrupt . . . . . . . . . . . . . . . . . . . 24-91
Host Controller Operational Model for FSTNs . . . . . . . . . . . . . . . . . . . . . . . . . . 24-94
Tracking Split Transaction Progress for Interrupt Transfers . . . . . . . . . . . . . . . . 24-97
Split Transaction Execution State Machine for Interrupt . . . . . . . . . . . . . . . . . . . 24-97
Periodic Interrupt—Do-Start-Split . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-98
Periodic Interrupt—Do-Complete-Split . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-99
Managing the QH[FrameTag] Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-102
Rebalancing the Periodic Schedule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-103
Split Transaction Scheduling Mechanisms for Isochronous. . . . . . . . . . . . . . . . 24-104
Split Transaction Execution State Machine for Isochronous . . . . . . . . . . . . . . . 24-109
Periodic Isochronous—Do-Start-Split . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-109
Periodic Isochronous—Do Complete Split. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-111
Complete-Split for Scheduling Boundary Cases 2a, 2b . . . . . . . . . . . . . . . . . . . 24-114
Split Transaction for Isochronous—Processing Examples. . . . . . . . . . . . . . . . . 24-115
Transaction Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-118
Serial Bus Babble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-118
Data Buffer Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-119
USB Interrupt (Interrupt on Completion (IOC)). . . . . . . . . . . . . . . . . . . . . . . . . 24-120
Short Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-120
Port Change Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-120
Frame List Rollover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-120
Interrupt on Async Advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-120
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor
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