MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 514
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MCF5253VM140J
Manufacturer Part Number
MCF5253VM140J
Description
IC MCU 2.1MIPS 140MHZ 225MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF525xr
Datasheets
1.MCF5253VM140J.pdf
(34 pages)
2.MCF5253VM140J.pdf
(8 pages)
3.MCF5253VM140J.pdf
(648 pages)
4.MCF5253VM140J.pdf
(2 pages)
Specifications of MCF5253VM140J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
140MHz
Connectivity
CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
Peripherals
DMA, WDT
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 70°C
Package / Case
225-MAPBGA
Processor Series
MCF525x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5253VM140J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Universal Serial Bus Interface
24.8.4
All Full-speed isochronous transfers through the internal transaction translator are managed using the siTD
data structure. This data structure satisfies the operational requirements for managing the split transaction
protocol.
24.8.4.1
DWord0 of a siTD is a pointer to the next schedule data structure.
24-52
1
31–12
I/O
ioc P
31–12
31
11–2
11–2
Hi Boss.
1–0
Bit
Bit
Host controller read/write; all others read-only.
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1
Buffer Pointer
Port Number
Buffer Pointer
0000
(Page 2)
Split Transaction Isochronous Transfer Descriptor (siTD)
Name
Name
Mult
Next Link Pointer
–
0000_0000_0000_00000
–
Figure 24-39. Split-Transaction Isochronous Transaction Descriptor (siTD)
Buffer Pointer (Page 0)
Buffer Pointer (Page 1)
This is a 4K aligned pointer to physical memory. Corresponds to memory address bits [31–12].
Reserved. This bit reserved for future use and should be cleared.
This field is used to indicate to the host controller the number of transactions that should be executed
per transaction description (for example, per micro-frame). The valid values are:
00 Reserved. A zero in this field yields undefined results.
01 One transaction to be issued for this endpoint per micro-frame
10 Two transactions to be issued for this endpoint per micro-frame
11 Three transactions to be issued for this endpoint per micro-frame
This is a 4K aligned pointer to physical memory. Corresponds to memory address bits [31–12].
Reserved. These bits reserved for future use and should be cleared.
Total Bytes to Transfer
0
Table 24-42. Buffer Pointer Page 2 (Plus)
Hub Address
Table 24-43. Buffer Pointer Page 3–6
Next Link Pointer
Back Pointer
MCF5253 Reference Manual, Rev. 1
1
15
µFrame C-prog-mask
0000
14 13 12 11 10
µFrame C-mask
Description
Description
EndPt
000_0000
9
1
8
Current Offset
0
7
6
µFrame S-mask
Device Address
5
Status
Freescale Semiconductor
4
TP
00
1
1
0000
3
1
2
T-count
Typ
1
T 0x00
T 0x18
0
1
Offset
0x0C
0x04
0x08
0x10
0x14
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