MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 583

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Advance bit in the USBSTS register. If the Interrupt on Async Advance Enable bit in the USBINTR
register is set, the host controller issues a hardware interrupt at the next interrupt threshold. A detailed
explanation of this feature is described in
Schedule.”
24.9.14.2.4 Host System Error
The host controller is a bus master and any interaction between the host controller and the system may
experience errors. The type of host error may be catastrophic to the host controller making it impossible
for the host controller to continue in a coherent fashion. Behavior for these types of errors is to halt the
host controller. Host-based error must result in the following actions:
Table 24-73
24.10 Device Data Structures
This section defines the interface data structures used to communicate control, status, and data between
Device Controller Driver (DCD) software and the Device Controller. The data structure definitions in this
chapter support a 32-bit memory buffer address space. The interface consists of device Queue Heads and
Transfer Descriptors.
Freescale Semiconductor
•
•
•
The Run/Stop bit in the USBCMD register is cleared.
The Host System Error and HCHalted bits in the USBSTS register are set:
If the Host System Error Enable bit in the USBINTR register is set, then the host controller issues
a hardware interrupt. This interrupt is not delayed to the next interrupt threshold.
summarizes the required actions taken on the various host errors.
Frame list pointer fetch (read)
siTD fetch (read)
siTD status write-back (write)
iTD fetch (read)
iTD status write-back (write)
qTD fetch (read)
qHD status write-back (write)
Data write
Data read
After a Host System Error, the software must reset the host controller using
HCReset in the USBCMD register before re-initializing and restarting the
host controller.
Cycle Type
Table 24-73. Summary Behavior on Host System Errors
MCF5253 Reference Manual, Rev. 1
Section 24.9.9.2, “Removing Queue Heads from Asynchronous
Master Abort
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
NOTE
Target Abort
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Data Phase Parity
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Universal Serial Bus Interface
24-121