MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 143

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

During the master reset period, the data bus is being tri-stated, the address bus is driven to any value, and
all other bus signals are driven to their negated state. Once RSTI negates, the bus stays in this state until
the core begins the first bus cycle for reset exception processing. A master reset causes any bus cycle
(including DRAM refresh cycle) to terminate. In addition, master reset initializes registers appropriately
for a reset exception.
If at power-on reset, the MCF5253 is configured to boot from external memory connected to CS0. Then
CS0 is configured to address the external boot ROM / Flash. The configuration for CS0 at this time is
hard-wired inside the MCF5253.
Configuration is summarized in
8.7.1
The software watchdog reset is performed anytime the executing software does not provide the correct
write sequence with the enable-control bit set. This reset helps recovery from runaway software or
nonterminated bus cycles. During the software watchdog reset period all signals are driven either to a high
impedance state or a negated state as appropriate.
Freescale Semiconductor
CRIN
VDD
RSTI
CS, OE
SDRAS, SDCAS
SDWE, BCLKE
D[31:16]
A[23:1], RW
Software Watchdog Reset
Cycle type
Port Size
Table 8-9. Power-On Reset Configuration for CS0
Table
Internal termination, 15 wait cycles
Burst inhibit asserted for both read and write cycles
Figure 8-16. Master Reset Timing
MCF5253 Reference Manual, Rev. 1
8-9.
CLKIN CYCLES
16 Bits
>16
Bus Operation
8-15