MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 445
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MCF5253VM140J
Manufacturer Part Number
MCF5253VM140J
Description
IC MCU 2.1MIPS 140MHZ 225MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF525xr
Datasheets
1.MCF5253VM140J.pdf
(34 pages)
2.MCF5253VM140J.pdf
(8 pages)
3.MCF5253VM140J.pdf
(648 pages)
4.MCF5253VM140J.pdf
(2 pages)
Specifications of MCF5253VM140J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
140MHz
Connectivity
CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
Peripherals
DMA, WDT
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 70°C
Package / Case
225-MAPBGA
Processor Series
MCF525x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5253VM140J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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23.5.2.2
Registers (ata_base +$0) till (ata_base + $17) contain timing parameters. These timing parameters control
the timing on the ATA bus as shown in details in the following illustrations:
Every timing parameter is 8-bit wide and can assume valid values between 1 and 255. Reset value is
always 1.
All figures in this section show timing registers.
23.5.2.2.1
See
the bit fields.
23.5.2.2.2
See
the bit fields.
Freescale Semiconductor
•
•
•
•
•
•
•
Figure 23-12
Figure 23-13
Address MBAR2 + 0x800 (TIME_OFF)
Reset
Little endian, 16-bit or 32-bit register:
— bits [7:0]: byte 0
— bits [15:8]: byte 1
— bits [23:8]: byte 2
— bits [31:24]: byte 3
Big endian, 32-bit register:
— bits [31:24]: byte 0
— bits [23:16]: byte 1
— bits [15:8]: byte 2
— bits [7:0]: byte 3
Big endian, 16-bit register:
— bits [15:8]: byte 0
— bits [7:0]: byte 1
Section 23.4.3.2, “PIO Mode
Section 23.4.3.3, “Timing in Multiword DMA
Section 23.4.3.4, “UDMA In Timing Diagrams”
Section 23.4.3.5, “UDMA Out Timing
W
R
Timing Registers
TIME_OFF Register
TIME_ON Register
0
7
for illustration of valid bits in the TIME_OFF Register and
for illustration of valid bits in the TIME_ON Register and
0
6
Figure 23-12. TIME_OFF Register
MCF5253 Reference Manual, Rev. 1
Timing”
0
5
Diagrams”
TIME_OFF[7:0]
0
4
Mode”
0
3
Advanced Technology Attachment Controller (ATA)
2
0
Table 23-8
Table 23-8
Access: User read/write
0
1
for description of
for description of
1
0
23-19
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