MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 521
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MCF5253VM140J
Manufacturer Part Number
MCF5253VM140J
Description
IC MCU 2.1MIPS 140MHZ 225MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF525xr
Datasheets
1.MCF5253VM140J.pdf
(34 pages)
2.MCF5253VM140J.pdf
(8 pages)
3.MCF5253VM140J.pdf
(648 pages)
4.MCF5253VM140J.pdf
(2 pages)
Specifications of MCF5253VM140J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
140MHz
Connectivity
CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
Peripherals
DMA, WDT
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 70°C
Package / Case
225-MAPBGA
Processor Series
MCF525x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5253VM140J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Freescale Semiconductor
11–10
9–8
Bit
PID Code
Name
Cerr
Error Counter. This field is a 2-bit down counter that keeps track of the number of consecutive errors
detected while executing this qTD. If this field is programmed with a non-zero value during set-up, the host
controller decrements the count and writes it back to the qTD if the transaction fails. If the counter counts
from one to zero, the host controller marks the qTD inactive, sets the Halted bit to a one, and error status
bit for the error that caused Cerr to decrement to zero. An interrupt will be generated if the USB Error
Interrupt Enable bit in the USBINTR register is set. If the host controller driver (HCD) software programs
this field to zero during set-up, the host controller will not count errors for this qTD and there will be no limit
on the retries of this qTD.
Note: Write-backs of intermediate execution state are to the queue head overlay area, not the qTD.
Transaction
Error
Data Buffer
Error
Stalled
Babble
Detected
No Error
This field is an encoding of the token, which should be used for transactions associated with this transfer
descriptor. Encodings are:
00 OUT Token generates token (E1H)
01 IN Token generates token (69H)
10 SETUP Token generates token (2DH) (undefined if endpoint is an Interrupt transfer type, for example.
11 Reserved.
µFrame S-mask field in the queue head is non-zero.)
Error
Table 24-53. qTD Token (DWord 2) (continued)
Yes
No
Note: The software must not program Cerr to a value of zero when the EPS field is
No
decremented
No
decremented
No
Schedule (and PIDCode indicates an IN or OUT) and a bus transaction completes and the
host controller does not detect a transaction error, then the host controller should reset Cerr
to extend the total number of errors for this transaction. For example, Cerr should be reset
with maximum value (0b11) on each successful completion of a transaction. The host
controller must never reset this field if the value at the start of the transaction is 0b00.
.
.
.
.
Data buffer errors are host problems. They don't count against the device's retries.
Detection of Babble or Stall automatically halts the queue head. Thus, count is not
Detection of Babble or Stall automatically halts the queue head. Thus, count is not
If the EPS field indicates a HS device or the queue head is in the Asynchronous
programmed with a value indicating a Full- or Low-speed device. This combination
could result in undefined behavior.
MCF5253 Reference Manual, Rev. 1
Description
Decrement Counter
Universal Serial Bus Interface
24-59
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