MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 590
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MCF5253VM140J
Manufacturer Part Number
MCF5253VM140J
Description
IC MCU 2.1MIPS 140MHZ 225MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF525xr
Datasheets
1.MCF5253VM140J.pdf
(34 pages)
2.MCF5253VM140J.pdf
(8 pages)
3.MCF5253VM140J.pdf
(648 pages)
4.MCF5253VM140J.pdf
(2 pages)
Specifications of MCF5253VM140J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
140MHz
Connectivity
CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
Peripherals
DMA, WDT
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 70°C
Package / Case
225-MAPBGA
Processor Series
MCF525x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5253VM140J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Universal Serial Bus Interface
It is also not necessary to initially prime Endpoint 0 because the first packet received will always be a setup
packet. The contents of the first setup packet will require a response in accordance with the USB 2.0
Specification, Chapter 9, Device Framework, command set.
24.11.2 Port State and Control
From a chip or system reset, the USB_DR enters the powered state. A transition from the powered state to
the attach state occurs when the Run/Stop bit is set to a '1'. After receiving a reset on the bus, the port will
enter the defaultFS or defaultHS state in accordance with the protocol reset described in Appendix C.2 of
the USB Specification Rev. 2.0. The following state diagram depicts the state of a USB 2.0 device.
24-128
6. Set Run/Stop bit to Run Mode.
Recommended: enable all device interrupts including: USBINT, USBERRINT, Port Change
Detect, USB Reset Received, DCSuspend.
For a list of available interrupts refer to USBINTR register description
USBSTS register description
After the Run bit is set, a device reset will occur. The DCD must monitor the reset event and set
the DEVICEADDR register, set the ENDPTCTRLx registers, and adjust the software state as
described in
Endpoint 0 is designed as a control endpoint only and does not need to be
configured using ENDPTCTRL0 register.
Section 24.11.2.1, “Bus
MCF5253 Reference Manual, Rev. 1
Table
24-16.
Reset.
NOTE
Table 24-17
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