MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 409

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

20.5.7
The BAAR register defines the address space for memory-referencing BDM commands. Bits [7:5] are
loaded directly from the BDM command, while the low-order 5 bits can be programmed from the external
development system. To maintain compatibility with the Rev. A implementation, this register is loaded any
time the AATR is written. The BAR is initialized to a value of $5, setting “supervisor data” as the default
address space.
20.5.8
The debug module supports concurrent operation of both the processor and most BDM commands. BDM
commands may be executed while the processor is running, except for the operations that access
processor/memory registers as follows:
Freescale Semiconductor
Reset
Field
SSM
W
IPI
R
Field
5
4
6–5
4–3
2–0
TM
SZ
TT
R
7
BDM Address Attribute Register (BAAR)
Concurrent BDM and Processor Operation
Table 20-22. Configuration/Status Register (CSR) Field Descriptions (continued)
R
0
7
If set, the Ignore Pending Interrupts bit forces the processor core to ignore any pending interrupt requests
signalled while executing in single-instruction-step mode.
If set, the Single-Step Mode bit forces the processor core to operate in a single-instruction-step mode. While
in this mode, the processor executes a single instruction and then halts. While halted, any of the BDM
commands may be executed. On receipt of the GO command, the processor executes the next instruction and
then halts again. This process continues until the single-instruction-step mode is disabled.
0 Write
1 Read
Size
00 Longword
01 Byte
10 Word
11 Reserved
Transfer Type
See the TT definition in the AATR description,
Transfer Modifier
See the TM definition in the AATR description,
Table 20-23. BDM Address Attribute (BAAR) Register Field Descriptions
0
6
Figure 20-38. BDM Address Attribute Register (BAAR)
SZ
MCF5253 Reference Manual, Rev. 1
0
5
0
4
Description
Section 20.5.2, “Address Attribute Trigger Register.”
Description
Section 20.5.2, “Address Attribute Trigger Register.”
TT
3
0
Background Debug Mode (BDM) Interface
1
2
Access: User write only
TM
0
1
1
0
20-39