MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 384

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Background Debug Mode (BDM) Interface
Result Data:
The contents of the selected register are returned as a longword value. The data is returned most significant
word first.
20.3.4.1.2
WAREG and WDREG write the operand longword data to the specified address or data register. All 32
register bits are altered by the write. A bus error response is returned if the CPU core is not halted.
Command Format:
Command Sequence:
Operand Data:
Longword data is written into the specified address or data register. The data is supplied most significant
word first.
Result Data:
Command complete status is indicated by returning the data $FFFF (with the status bit cleared) when the
register write is complete.
20.3.4.1.3
The READ command reads the operand data from the memory location specified by the longword address.
The address space is defined by the contents of the low-order 5 bits {TT, TM} of the BDM Address
Attribute Register (BAAR). The hardware forces the low-order bits of the address to zeros for word and
longword accesses to ensure that operands are always accessed on natural boundaries: words on
0-modulo-2 addresses, longwords on 0-modulo-4 addresses.
20-14
Write Address/Data Register (WAREG and WDREG)
Read Memory Location (READ)
WDREG/WAREG
15
???
14
$2
Figure 20-10. Write A/D Register Command Sequence
13
12
Table 20-8. WAREG/WDREG Command
11
MCF5253 Reference Manual, Rev. 1
10
“Not Ready”
$0
MS Data
BERR
XXX
9
DATA [31:16]
DATA [15:0]
8
7
“Not Ready”
“Not Ready”
Next CMD
LS Data
6
$8
5
4
A/D
“Cmd Complete”
3
Next CMD
2
REGISTER
1
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0