MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 66

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

ColdFire Core
3.2.2
The eMAC provides a variety of program-visible registers:
3.2.2.1
The eMAC unit supports the integer multiply operations defined by the baseline ColdFire architecture, as
well as the multiply-accumulate instructions.
3-4
Multiply Accumulate with
Field
Store MAC Status Reg
Load MAC Status Reg
Store MACSR to CCR
Store MAC Mask Reg
Load MAC Mask Reg
Multiply Accumulate
1
0
Store Accumulator
•
•
•
•
Copy Accumulator
Load Accumulator
Multiply Unsigned
Multiply Signed
Command
Four 48-bit accumulators (Raccx = Racc0, Racc1, Racc2, Racc3)
Eight 8-bit accumulator extensions (2 per accumulator), packaged as two 32-bit values for load and
store operations (Raccext01, Raccext23)
One 16-bit Mask Register (Rmask)
One 32-bit Status Register (MACSR) including four indicator bits signaling product or
accumulation overflow (one for each accumulator: PAV0, PAV1, PAV2, PAV3)
Load
Code
C
V
Enhanced Multiply Accumulate Module (eMAC) User Memory Map
and Register Description
eMAC Instruction Set Summary
Overflow condition code bit. Set if an arithmetic overflow occurs, implying that the result cannot be
represented in the operand size; otherwise cleared.
Carry condition code bit. Set if a carry-out of the data operand msb occurs for an addition or if a borrow
occurs in a subtraction; otherwise cleared.
MSAC Ry,RxSF,Rw,Raccx
MOV.L {Ry,#imm},MACSR
MOV.L {Ry,#imm},Rmask
MAC Ry,RxSF,Rw,Raccx
MOV.L {Ry,#imm},Raccx
Table 3-2. CCR Register Field Description (continued)
MSAC Ry,RxSF,Raccx
MAC Ry,RxSF,Raccx
MOV.L MACSR,CCR
MOV.L Raccy,Raccx
MOV.L MACSR,Rx
MOV.L Rmask,Rx
MOV.L Raccx,Rx
MULS <ea>y,Dx
MULU <ea>y,Dx
Mnemonic
Table 3-3. eMAC Instruction Summary
MCF5253 Reference Manual, Rev. 1
Table 3-3
Multiplies two signed operands yielding a signed result
Multiplies two unsigned operands yielding an unsigned result
Multiplies two operands, then adds/subtracts the product to/from an
accumulator
Multiplies two operands, then combines the product to an
accumulator while loading a register with the memory operand
Writes the contents of an accumulator to a CPU register
Copies a 48-bit accumulator
Writes a value to the MAC status register
Write the contents of the MAC status register to a CPU register
Write the contents of the MAC status register to the
processor’s CCR register
Writes a value to the MAC Mask Register
Writes the contents of the MAC mask register to a CPU
register
Loads an accumulator with a 32-bit operand
summarizes the eMAC unit instruction set.
Description
Description
Freescale Semiconductor