HD64F3684FP Renesas Electronics America, HD64F3684FP Datasheet

IC H8 MCU FLASH 32K 64LQFP

HD64F3684FP

Manufacturer Part Number
HD64F3684FP
Description
IC H8 MCU FLASH 32K 64LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of HD64F3684FP

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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To our customers,
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
On April 1
st
, 2010, NEC Electronics Corporation merged with Renesas Technology
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Renesas Electronics Corporation
st
, 2010

HD64F3684FP Summary of contents

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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...

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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...

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H8/3687Group 16 Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by ...

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Rev.5.00 Nov. 02, 2005 Page ii of xxxii ...

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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...

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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...

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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip ...

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The H8/3687 Group are single-chip microcomputers made up of the high-speed H8/300H CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set that is compatible ...

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The NMI pin is reserved for the E7 or E8, and cannot be used. 2. Pins P85, P86, and P87 cannot be used. In order to use these pins, additional hardware must be provided on the user board. 3. ...

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Application notes: Document Title H8S, H8/300 Series C/C++ Compiler Package Application Note Single Power Supply F-ZTAT Rev.5.00 Nov. 02, 2005 Page viii of xxxii TM On-Board Programming Document No. REJ05B0464 ADE-502-055 ...

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Rev.5.00 Nov. 02, 2005 Page ix of xxxii ...

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Section 1 Overview ............................................................................................... 1 1.1 Features.................................................................................................................................. 1 1.2 Internal Block Diagram.......................................................................................................... 3 1.3 Pin Arrangement .................................................................................................................... 5 1.4 Pin Functions ......................................................................................................................... 7 Section 2 CPU ..................................................................................................... 11 2.1 Address Space and Memory Map ........................................................................................ 12 2.2 Register Configuration......................................................................................................... 15 ...

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Interrupt Flag Register 1 (IRR1)............................................................................. 53 3.2.6 Interrupt Flag Register 2 (IRR2)............................................................................. 55 3.2.7 Wakeup Interrupt Flag Register (IWPR) ................................................................ 55 3.3 Reset Exception Handling.................................................................................................... 57 3.4 Interrupt Exception Handling............................................................................................... 57 3.4.1 External Interrupts .................................................................................................. 57 3.4.2 Internal Interrupts ...

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System Control Register 2 (SYSCR2) .................................................................... 78 6.1.3 Module Standby Control Register 1 (MSTCR1) .................................................... 79 6.1.4 Module Standby Control Register 2 (MSTCR2) .................................................... 80 6.2 Mode Transitions and States of LSI..................................................................................... 80 6.2.1 Sleep Mode ............................................................................................................. 84 6.2.2 ...

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Port Mode Register 1 (PMR1) .............................................................................. 110 9.1.2 Port Control Register 1 (PCR1) ............................................................................ 111 9.1.3 Port Data Register 1 (PDR1)................................................................................. 111 9.1.4 Port Pull-Up Control Register 1 (PUCR1)............................................................ 112 9.1.5 Pin Functions ........................................................................................................ 112 9.2 Port 2.................................................................................................................................. 115 ...

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Minute Data Register (RMINDR) ........................................................................ 144 10.3.3 Hour Data Register (RHRDR) .............................................................................. 145 10.3.4 Day-of-Week Data Register (RWKDR) ............................................................... 146 10.3.5 RTC Control Register 1 (RTCCR1) ..................................................................... 147 10.3.6 RTC Control Register 2 (RTCCR2) ..................................................................... 148 10.3.7 Clock Source ...

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Section 13 Timer Z ............................................................................................175 13.1 Features.............................................................................................................................. 175 13.2 Input/Output Pins ............................................................................................................... 180 13.3 Register Descriptions ......................................................................................................... 181 13.3.1 Timer Start Register (TSTR) ................................................................................ 182 13.3.2 Timer Mode Register (TMDR) ............................................................................. 183 13.3.3 Timer PWM Mode Register (TPMR) ................................................................... 184 ...

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Section 15 14-Bit PWM .................................................................................... 255 15.1 Features.............................................................................................................................. 255 15.2 Input/Output Pin ................................................................................................................ 256 15.3 Register Descriptions......................................................................................................... 256 15.3.1 PWM Control Register (PWCR) .......................................................................... 256 15.3.2 PWM Data Registers U and L (PWDRU, PWDRL)............................................. 257 15.4 Operation ........................................................................................................................... 257 Section ...

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Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ............................................................................ 301 2 Section Bus Interface 2 (IIC2) ................................................................303 17.1 Features.............................................................................................................................. 303 17.2 Input/Output Pins ............................................................................................................... 305 17.3 Register Descriptions ......................................................................................................... 305 2 17.3 ...

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Scan Mode ............................................................................................................ 343 18.4.3 Input Sampling and A/D Conversion Time .......................................................... 344 18.4.4 External Trigger Input Timing.............................................................................. 345 18.5 A/D Conversion Accuracy Definitions .............................................................................. 346 18.6 Usage Notes ....................................................................................................................... 348 18.6.1 Permissible Signal Source Impedance .................................................................. 348 18.6.2 ...

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Section 22 List of Registers ...............................................................................373 22.1 Register Addresses (Address Order).................................................................................. 374 22.2 Register Bits....................................................................................................................... 381 22.3 Registers States in Each Operating Mode .......................................................................... 386 Section 23 Electrical Characteristics .................................................................391 23.1 Absolute Maximum Ratings .............................................................................................. 391 23.2 Electrical Characteristics (F-ZTAT™ ...

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Appendix C Product Code Lineup .................................................................... 486 Appendix D Package Dimensions ..................................................................... 488 Appendix E EEPROM Stacked-Structure Cross-Sectional View ..................... 490 Main Revisions and Additions in this Edition..................................................... 491 Index .................................................................................................................. 497 Rev.5.00 Nov. 02, 2005 Page xx of xxxii ...

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Section 1 Overview Figure 1.1 Internal Block Diagram of H8/3687 Group of F-ZTAT and Mask-ROM Versions.............................................................................................. 3 Figure 1.2 Internal Block Diagram of H8/3687N (EEPROM Stacked Version) ............................ 4 Figure 1.3 Pin Arrangement of H8/3687 Group of F-ZTAT (FP-64E, FP-64A) ...

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Section 5 Clock Pulse Generators Figure 5.1 Block Diagram of Clock Pulse Generators.................................................................. 69 Figure 5.2 Block Diagram of System Clock Generator ................................................................ 70 Figure 5.3 Typical Connection to Crystal Resonator.................................................................... 70 Figure 5.4 Equivalent Circuit of Crystal Resonator...................................................................... 70 ...

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Figure 12.2 Increment Timing with Internal Clock .................................................................... 167 Figure 12.3 Increment Timing with External Clock ................................................................... 167 Figure 12.4 OVF Set Timing ...................................................................................................... 167 Figure 12.5 CMFA and CMFB Set Timing ................................................................................ 168 Figure 12.6 TMOV Output Timing ............................................................................................ ...

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Figure 13.27 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 1) ...... 219 Figure 13.28 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 0) ...... 220 Figure 13.29 Example of Complementar y PWM Mode ...

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Figure 13.59 When Compare Match and Bit Manipulation Instruction to TOCR Occur at the Same Timing..................................................................................... 250 Section 14 Watchdog Timer Figure 14.1 Block Diagram of Watchdog Timer ........................................................................ 251 Figure 14.2 Watchdog Timer Operation Example...................................................................... 254 Section 15 14-Bit ...

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Figure 17.2 External Circuit Connections of I/O Pins ................................................................ 305 2 Figure 17 Bus Formats ...................................................................................................... 318 2 Figure 17 Bus Timing........................................................................................................ 318 Figure 17.5 Master Transmit Mode Operation Timing (1)......................................................... 320 Figure 17.6 Master Transmit ...

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Figure 20.4 Operational Timing of LVDI Circuit....................................................................... 368 Figure 20.5 Timing for Operation/Release of Low-Voltage Detection Circuit .......................... 369 Section 21 Power Supply Circuit Figure 21.1 Power Supply Connection when Internal Step-Down Circuit is Used .................... 371 Figure 21.2 Power ...

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Appendix D Package Dimensions Figure D.1 FP-64E Package Dimensions ................................................................................... 488 Figure D.2 FP-64A Package Dimensions ................................................................................... 489 Appendix E EEPROM Stacked-Structure Cross-Sectional View Figure E.1 EEPROM Stacked-Structure Cross-Sectional View ................................................. 490 Rev.5.00 Nov. 02, 2005 Page xxviii of xxxii ...

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Section 1 Overview Table 1.1 Pin Functions ............................................................................................................ 7 Section 2 CPU Table 2.1 Operation Notation ................................................................................................. 22 Table 2.2 Data Transfer Instructions....................................................................................... 23 Table 2.3 Arithmetic Operations Instructions (1) ................................................................... 24 Table 2.3 Arithmetic Operations Instructions (2) ................................................................... 25 ...

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Table 7.4 Reprogram Data Computation Table .................................................................... 102 Table 7.5 Additional-Program Data Computation Table ...................................................... 102 Table 7.6 Programming Time ............................................................................................... 102 Table 7.7 Flash Memory Operating States............................................................................ 106 Section 10 Realtime Clock (RTC) Table 10.1 Pin Configuration.................................................................................................. 142 Table ...

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Section Bus Interface 2 (IIC2) 2 Table 17 Bus Interface Pins........................................................................................... 305 Table 17.2 Transfer Rate ........................................................................................................ 307 Table 17.3 Interrupt Requests ................................................................................................. 334 Table 17.4 Time for Monitoring SCL..................................................................................... 335 Section 18 A/D ...

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Table 23.20 Power-On Reset Circuit Characteristics ........................................................... 428 Appendix A Instruction Set Table A.1 Instruction Set....................................................................................................... 435 Table A.2 Operation Code Map (1) ....................................................................................... 448 Table A.2 Operation Code Map (2) ....................................................................................... 449 Table A.2 Operation Code Map (3) ....................................................................................... ...

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Features High-speed H8/300H central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 CPU on an object level Sixteen 16-bit general registers 62 basic instructions Various peripheral functions RTC (can be used as a free running counter) Timer ...

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Section 1 Overview On-chip memory Product Classification Flash memory version H8/3687F HD64F3687 HD64F3687G TM (F-ZTAT version) H8/3684F HD64F3684 HD64F3684G Mask-ROM version H8/3687 H8/3686 H8/3685 H8/3684 H8/3683 H8/3682 EEPROM Flash H8/3687N stacked memory version version (512 bytes) Mask-ROM version General I/O ...

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Internal Block Diagram Subclock generator P10/TMOW P11/PWM P12 P14/IRQ0 P15/IRQ1/TMIB1 P16/IRQ2 P17/IRQ3/TRGV P20/SCK3 P21/RXD P22/TXD P23 P24 P30 P31 P32 P33 P34 P35 P36 P37 P57/SCL P56/SDA P55/WKP5/ADTRG P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0 Figure 1.1 Internal Block Diagram of ...

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Section 1 Overview Subclock generator P10/TMOW P11/PWM P12 P14/IRQ0 P15/IRQ1/TMIB1 P16/IRQ2 P17/IRQ3/TRGV P20/SCK3 P21/RXD P22/TXD P23 P24 P30 P31 P32 P33 P34 P35 P36 P37 P57/SCL P56/SDA P55/WKP5/ADTRG P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0 Note: The HD64N3687G is a stacked-structure product ...

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Pin Arrangement P71/RXD_2 50 P72/TXD_2 51 P14/IRQ0 P15/IRQ1/TMIB1 52 P16/IRQ2 53 54 P17/IRQ3/TRGV 55 P33 56 P32 57 P31 58 P30 59 ...

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Section 1 Overview P71/RXD_2 50 P72/TXD_2 51 P14/IRQ0 52 P15/IRQ1/TMIB1 53 P16/IRQ2 54 P17/IRQ3/TRGV P33 55 56 P32 57 P31 58 P30 59 ...

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Pin Functions Table 1.1 Pin Functions Pin No. FP-64E Type Symbol FP-64A Power source pins Clock pins OSC1 11 OSC2 RES System ...

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Section 1 Overview Pin No. FP-64E Type Symbol FP-64A Timer V TMOV 30 TMCIV 29 TMRIV 28 TRGV 54 Timer Z FTIOA0 36 FTIOB0 34 FTIOC0 33 FTIOD0 32 FTIOA1 37 FTIOB1 FTIOD1 14-bit PWM PWM ...

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Pin No. FP-64E Type Symbol FP-64A I/O ports PB7 to PB0 P17 to P14 54, P12 to P10 P24 to P20 31 I/O P37 to P30 15 ...

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Section 1 Overview Rev.5.00 Nov. 02, 2005 Page 10 of 500 REJ09B0027-0500 ...

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This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with the H8/300CPU, and supports only normal mode, which has a 64-kbyte address space. Upward-compatible with H8/300 CPUs Can execute H8/300 CPUs object programs Additional eight ...

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Section 2 CPU 2.1 Address Space and Memory Map The address space of this LSI is 64 kbytes, which includes the program area and the data area. Figures 2.1 show the memory map. HD64N3687G HD64F3687 HD64F3687G (Flash memory version) H'0000 ...

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HD6433684 HD6433684G (Mask-ROM version) H'0000 H'0000 Interrupt vector H'0041 H'0041 H'0042 H'0042 On-chip ROM (32 kbytes) H'7FFF H'9FFF Not used H'E800 H'E800 On-chip RAM (2 kbytes) H'EFFF H'EFFF Not used H'F700 H'F700 Internal I/O register H'F77F H'F77F Not used H'FB80 ...

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Section 2 CPU Rev.5.00 Nov. 02, 2005 Page 14 of 500 REJ09B0027-0500 HD64N3687G HD6483687G (On-chip EEPROM module) H'0000 User area (512 bytes) H'01FF Not used H'FF09 Slave address register Not used Figure 2.1 Memory Map (3) ...

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Register Configuration The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition-code register (CCR). ...

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Section 2 CPU 2.2.1 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a ...

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SP (ER7) Figure 2.4 Relationship between Stack Pointer and Stack Area 2.2.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), ...

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Section 2 CPU Initial Bit Bit Name Value Undefined R Undefined R Undefined R Undefined R Undefined R Undefined R Undefined R/W Rev.5.00 ...

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Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte operand data. ...

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Section 2 CPU Data Type General Data Format Register Word data Rn Word data En 15 MSB Longword ERn data 31 MSB [Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: ...

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Memory Data Formats Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address attempt is made ...

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Section 2 CPU 2.4 Instruction Set 2.4.1 Table of Instructions Classified by Function The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined ...

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Table 2.2 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B (EAs) Cannot be used in this ...

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Section 2 CPU Table 2.3 Arithmetic Operations Instructions (1) Instruction Size* Function ADD B/W/L Rd ± Rs SUB Performs addition or subtraction on data in two general registers immediate data and data in a general register (immediate byte ...

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Table 2.3 Arithmetic Operations Instructions (2) Instruction Size* Function DIVXS B/W Rd ÷ Rs Performs signed division on data in two general registers: either 16 bits ÷ 8 bits quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – ...

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Section 2 CPU Table 2.4 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd Performs a logical OR operation on a ...

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Table 2.6 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of ...

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Section 2 CPU Table 2.6 Bit Manipulation Instructions (2) Instruction Size* Function BXOR B C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B ...

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Table 2.7 Branch Instructions Instruction Size Function Bcc* Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE BLT ...

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Section 2 CPU Table 2.8 System Control Instructions Instruction Size* Function TRAPA Starts trap-instruction exception handling. RTE Returns from an exception-handling routine. SLEEP Causes a transition to a power-down state. LDC B/W (EAs) Moves the source operand contents to the ...

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Table 2.9 Block Data Transfer Instructions Instruction Size Function EEPMOV.B if R4L else next; EEPMOV else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L ...

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Section 2 CPU 2.4.2 Basic Instruction Formats H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.7 shows ...

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Addressing Modes and Effective Address Calculation The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits. 2.5.1 Addressing Modes The H8/300H CPU ...

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Section 2 CPU Register Indirect @ERn The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of the operand on memory. Register Indirect with Displacement @(d:16, ERn) or @(d:24, ...

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Table 2.11 Absolute Address Access Ranges Absolute Address 8 bits (@aa:8) 16 bits (@aa:16) 24 bits (@aa:24) Immediate #xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, ...

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Section 2 CPU Figure 2.8 Branch Address Specification in Memory Indirect Mode 2.5.2 Effective Address Calculation Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI the upper 8 bits of the effective address are ...

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Table 2.12 Effective Address Calculation (2) Addressing Mode and Instruction Format Absolute address Immediate [Legend] r, rm,rn: Register field op: Operation field disp: Displacement IMM: Immediate data abs: Absolute address Effective Address Calculation PC contents Sign extension Memory contents Rev.5.00 ...

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Section 2 CPU 2.6 Basic Bus Cycle CPU operation is synchronized by a system clock ( ) or a subclock ( edge the next rising edge is called one state. A bus cycle consists of two states ...

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On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and number of accessing ...

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Section 2 CPU 2.7 CPU States There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active mode and subactive mode. For the program halt state, there are ...

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Reset state Reset occurs Program halt state 2.8 Usage Notes 2.8.1 Notes on Data Access to Empty Areas The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to ...

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Section 2 CPU Bit manipulation for two registers assigned to the same address Example 1: Bit manipulation for the timer load register and timer counter (Applicable for timer B1 in the H8/3687 Group.) Figure 2.13 shows an example of a ...

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Prior to executing BSET instruction P57 P56 Input/output Input Input Pin state Low High level level PCR5 0 0 PDR5 1 0 BSET instruction executed instruction BSET #0, @PDR5 After executing BSET instruction P57 P56 Input/output Input Input Pin state ...

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Section 2 CPU Prior to executing BSET instruction MOV.B #80, R0L MOV.B R0L, @RAM0 MOV.B R0L, @PDR5 P57 P56 Input/output Input Input Pin state Low High level level PCR5 0 0 PDR5 1 0 RAM0 1 0 BSET instruction executed ...

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Prior to executing BCLR instruction P57 P56 Input/output Input Input Pin state Low High level level PCR5 0 0 PDR5 1 0 BCLR instruction executed BCLR #0, @PCR5 After executing BCLR instruction P57 P56 Input/output Output Output Pin state Low ...

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Section 2 CPU Prior to executing BCLR instruction MOV.B #3F, R0L MOV.B R0L, @RAM0 MOV.B R0L, @PCR5 P57 P56 Input/output Input Input Pin state Low High level level PCR5 0 0 PDR5 1 0 RAM0 0 0 BCLR instruction executed ...

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Section 3 Exception Handling Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts. Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES pin. ...

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Section 3 Exception Handling 3.1 Exception Sources and Vector Address Table 3.1 shows the vector addresses and priority of each exception handling. When more than one interrupt is requested, handling is performed from the interrupt with the highest priority. Table ...

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Relative Module Exception Sources IIC2 Transmit data empty Transmit end Receive data full Arbitration lost/Overrun error NACK detection Stop conditions detected A/D converter A/D conversion end Timer Z Compare match/input capture Timer Z overflow Compare match/input capture ...

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Section 3 Exception Handling 3.2.1 Interrupt Edge Select Register 1 (IEGR1) IEGR1 selects the direction of an edge that generates interrupt requests of pins NMI and IRQ3 to IRQ0. Initial Bit Bit Name Value 7 NMIEG ...

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Interrupt Edge Select Register 2 (IEGR2) IEGR2 selects the direction of an edge that generates interrupt requests of the pins ADTRG and WKP5 to WKP0. Initial Bit Bit Name Value 7, 6 All 1 5 WPEG5 0 4 WPEG4 ...

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Section 3 Exception Handling 3.2.3 Interrupt Enable Register 1 (IENR1) IENR1 enables direct transition interrupts, RTC interrupts, and external pin interrupts. Initial Bit Bit Name Value 7 IENDT 0 6 IENTA 0 5 IENWP IEN3 0 ...

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Interrupt Enable Register 2 (IENR2) IENR2 enables, timer B1 overflow interrupts. Initial Bit Bit Name Value 7, 6 All 0 5 IENTB1 All 1 When disabling interrupts by clearing bits in an interrupt enable register, ...

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Section 3 Exception Handling Initial Bit Bit Name Value 5, 4 All 1 3 IRRI3 0 2 IRRI2 0 1 IRRI1 0 0 IRRl0 0 Rev.5.00 Nov. 02, 2005 Page 54 of 500 REJ09B0027-0500 R/W Description Reserved These bits are ...

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Interrupt Flag Register 2 (IRR2) IRR2 is a status flag register for timer B1 overflow interrupts. Initial Bit Bit Name Value 7, 6 All 0 5 IRRTB1 All 1 3.2.7 Wakeup Interrupt Flag Register (IWPR) ...

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Section 3 Exception Handling Initial Bit Bit Name Value 3 IWPF3 0 2 IWPF2 0 1 IWPF1 0 0 IWPF0 0 Rev.5.00 Nov. 02, 2005 Page 56 of 500 REJ09B0027-0500 R/W Description R/W WKP3 Interrupt Request Flag [Setting condition] When ...

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Reset Exception Handling When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure ...

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Section 3 Exception Handling WKP5 to WKP0 Interrupts WKP5 to WKP0 interrupts are requested by input signals to pins WKP5 to WKP0. These six interrupts have the same vector addresses, and are detected individually by either rising edge sensing or ...

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Internal Interrupts Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to enable or disable the interrupt. For RTC interrupt requests and direct transfer interrupt requests generated by execution of a ...

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Section 3 Exception Handling SP – – – – (R7) Stack area Prior to start of interrupt exception handling [Legend Upper 8 bits of program counter (PC ...

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Figure 3.3 Interrupt Sequence Section 3 Exception Handling Rev.5.00 Nov. 02, 2005 Page 61 of 500 REJ09B0027-0500 ...

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Section 3 Exception Handling 3.5 Usage Notes 3.5.1 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program ...

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Section 4 Address Break The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR. Break conditions that can ...

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Section 4 Address Break Break address register (BARH, BARL) Break data register (BDRH, BDRL) 4.1.1 Address Break Control Register (ABRKCR) ABRKCR sets address break conditions. Initial Bit Bit Name Value 7 RTINTE 1 6 CSEL1 0 5 CSEL0 0 4 ...

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When an address break is set in the data read cycle or data write cycle, the data bus used will depend on the combination of the byte/word access and address. Table 4.1 shows the access and data bus used. When ...

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Section 4 Address Break 4.1.4 Break Data Registers (BDRH, BDRL) BDRH and BDRL are 16-bit read/write registers that set the data for generating an address break interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is compared with ...

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When the address break is specified in the data read cycle Register setting Program • ABRKCR = H'A0 0258 • BAR = H'025A 025A * 025C 0260 0262 : MOV MOV instruc- instruc- tion 1 tion 2 prefetch prefetch Address ...

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Section 4 Address Break Rev.5.00 Nov. 02, 2005 Page 68 of 500 REJ09B0027-0500 ...

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Section 5 Clock Pulse Generators Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator, a duty ...

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Section 5 Clock Pulse Generators 5.1 System Clock Generator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator providing external clock input. Figure 5.2 shows a block diagram of ...

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Table 5.1 Crystal Resonator Parameters Frequency (MHz (max) 500 S C (max 5.1.2 Connecting Ceramic Resonator Figure 5.5 shows a typical method of connecting a ceramic resonator. Figure 5.5 Typical Connection to Ceramic Resonator 5.1.3 ...

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Section 5 Clock Pulse Generators 5.2 Subclock Generator Figure 5.7 shows a block diagram of the subclock generator. Figure 5.7 Block Diagram of Subclock Generator 5.2.1 Connecting 32.768-kHz Crystal Resonator Clock pulses can be supplied to the subclock divider by ...

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Pin Connection when Not Using Subclock When the subclock is not used, connect pin X figure 5.10. Figure 5.10 Pin Connection when not Using Subclock 5.3 Prescalers 5.3.1 Prescaler S Prescaler 13-bit counter using the system ...

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Section 5 Clock Pulse Generators 5.4 Usage Notes 5.4.1 Note on Resonators Resonator characteristics are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Resonator circuit constants will ...

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Section 6 Power-Down Modes This LSI has six modes of operation after a reset. These include a normal active mode and four power-down modes, in which power consumption is significantly reduced. Module standby mode reduces power consumption by selectively halting ...

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Section 6 Power-Down Modes 6.1.1 System Control Register 1 (SYSCR1) SYSCR1 controls the power-down modes, as well as SYSCR2. Initial Bit Bit Name Value 7 SSBY 0 6 STS2 0 5 STS1 0 4 STS0 0 3 NESEL 0 2 ...

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Table 6.1 Operating Frequency and Waiting Time Bit Name STS2 STS1 STS0 Waiting Time 8,192 states 1 16,384 states 1 0 32,768 states 1 65,536 states 131,072 states 1 1,024 states 1 0 128 ...

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Section 6 Power-Down Modes 6.1.2 System Control Register 2 (SYSCR2) SYSCR2 controls the power-down modes, as well as SYSCR1. Initial Bit Bit Name Value 7 SMSEL 0 6 LSON 0 5 DTON 0 4 MA2 0 3 MA1 0 2 ...

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Module Standby Control Register 1 (MSTCR1) MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units. Initial Bit Bit Name Value MSTIIC 0 5 MSTS3 0 4 MSTAD 0 3 MSTWD 0 ...

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Section 6 Power-Down Modes 6.1.4 Module Standby Control Register 2 (MSTCR2) MSTCR2 allows the on-chip peripheral modules to enter a standby state in module units. Initial Bit Bit Name Value 7 MSTS3_2 All 0 4 MSTTB1 0 ...

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Reset state Program halt state SLEEP instruction Standby mode Interrupt SLEEP instruction Notes make a transition to another mode by an interrupt, make sure interrupt handling is after the interrupt is accepted. 2. Details on the mode transition ...

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Section 6 Power-Down Modes Table 6.2 Transition Mode after SLEEP Instruction Execution and Transition Mode due to Interrupt DTON SSBY SMSEL Legend: X: Don’t care. * When a state ...

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Table 6.3 Internal State in Each Operating Mode Function Active Mode System clock oscillator Functioning Subclock oscillator Functioning CPU Instructions Functioning operations Registers Functioning RAM Functioning IO ports Functioning External IRQ3 to IRQ0 Functioning interrupts WKP5 to Functioning WKP0 Peripheral ...

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Section 6 Power-Down Modes 6.2.1 Sleep Mode In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock frequency set by the MA2, MA1, and MA0 bits in SYSCR2. CPU register contents are retained. When ...

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LSON bit in SYSCR2 is 0, and a transition is made to subactive mode when the bit is 1. After the time set in bits STS2 to STS0 in SYSCR1 ...

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Section 6 Power-Down Modes 6.4 Direct Transition The CPU can execute programs in two modes: active and subactive modes. A direct transition is a transition between these two modes without stopping program execution. A direct transition can be made by ...

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Example Direct transition time = ( 8tw + (8192 + 14) tosc = 24tw + 8206tosc (when the CPU operating clock of Legend tosc: OSC clock cycle time tw: Watch clock cycle time tcyc: System clock ( ) ...

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Section 6 Power-Down Modes Rev.5.00 Nov. 02, 2005 Page 88 of 500 REJ09B0027-0500 ...

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The features of the 56-kbyte or 32-kbyte flash memories built into the flash memory (F-ZTAT) version are summarized below. Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The flash memory ...

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Section 7 ROM H'0000 Erase unit H'0080 1 kbyte H'0380 H'0400 Erase unit H'0480 1 kbyte H'0780 H'0800 Erase unit H'0880 1 kbyte H'0B80 H'0C00 Erase unit H'0C80 1 kbyte H'0F80 H'1000 Erase unit H'1080 28 kbytes H'7F80 H'8000 Erase ...

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Register Descriptions The flash memory has the following registers. Flash memory control register 1 (FLMCR1) Flash memory control register 2 (FLMCR2) Erase block register 1 (EBR1) Flash memory power control register (FLPWCR) Flash memory enable register (FENR) 7.2.1 Flash ...

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Section 7 ROM Initial Bit Bit Name Value 7.2.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a read-only ...

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Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 not set more than one bit at a time, as this will ...

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Section 7 ROM 7.2.4 Flash Memory Power Control Register (FLPWCR) FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. There are two modes: mode in which operation of the power ...

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On-Board Programming Modes There are two modes for programming/erasing of the flash memory; boot mode, which enables on- board programming/erasing, and programmer mode, in which programming/erasing is performed with a PROM programmer. On-board programming/erasing can also be performed in ...

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Section 7 ROM pulled up on the board if necessary. After the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. 4. After matching the bit rates, the chip transmits one ...

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Table 7.2 Boot Mode Operation Host Operation Processing Contents Continuously transmits data H'00 at specified bit rate. Transmits data H'55 when data H'00 is received error-free. Boot program erase error H'AA reception Transmits number of bytes (N) of programming control ...

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Section 7 ROM Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 19,200 bps MHz 9,600 bps MHz 4,800 ...

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Reset-start Program/erase? Yes Transfer user program/erase control program to RAM Branch to user program/erase control program in RAM Execute user program/erase control program (flash memory rewrite) Branch to flash memory application program Figure 7.2 Programming/Erasing Flowchart Example in User Program ...

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Section 7 ROM 7.4 Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the on- board programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the ...

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The maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000. Write pulse application subroutine Apply Write Pulse WDT enable Set PSU bit in FLMCR1 Wait 50 s Set P bit in FLMCR1 Wait (Wait ...

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Section 7 ROM Table 7.4 Reprogram Data Computation Table Program Data Verify Data Table 7.5 Additional-Program Data Computation Table Reprogram Data Verify Data Table ...

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For a dummy write to a verify address, write 1-byte data H' address whose lower two bits are B'00. Verify data can be read in longwords from the address to which a dummy write was performed. 6. ...

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Section 7 ROM Increment address Note: *The RTS instruction must not be used during a period between dummy writing of H' verify address and verify data reading. Figure 7.4 Erase/Erase-Verify Flowchart Rev.5.00 Nov. 02, 2005 Page 104 of ...

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Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because ...

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Section 7 ROM entered by re-setting the bit. However, PV and EV bit settings are retained, and a transition can be made to verify mode. Error protection can be cleared only by a reset. 7.6 Programmer Mode ...

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This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte data and word data. Product Classification Flash memory version H8/3687F TM ...

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Section 8 RAM Rev.5.00 Nov. 02, 2005 Page 108 of 500 REJ09B0027-0500 ...

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The group of this LSI has forty-five general I/O ports (forty-three general I/O ports in the H8/3687N) and eight general input-only ports. Port large current port, which can drive 20 mA (@V = 1.5 V) when a ...

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Section 9 I/O Ports 9.1.1 Port Mode Register 1 (PMR1) PMR1 switches the functions of pins in port 1 and port 2. Initial Bit Bit Name Value 7 IRQ3 0 6 IRQ2 0 5 IRQ1 0 4 IRQ0 0 3 ...

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Port Control Register 1 (PCR1) PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1. Initial Bit Bit Name Value 7 PCR17 0 6 PCR16 0 5 PCR15 0 4 PCR14 ...

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Section 9 I/O Ports 9.1.4 Port Pull-Up Control Register 1 (PUCR1) PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports. Initial Bit Bit Name Value 7 PUCR17 0 6 PUCR16 0 5 PUCR15 ...

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P16/IRQ2 pin Register PMR1 PCR1 Bit Name IRQ2 PCR16 Setting value Legend: X: Don't care. P15/IRQ1/TMIB1 pin Register PMR1 PCR1 Bit Name IRQ1 PCR15 Setting value Legend: X: Don't care. ...

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Section 9 I/O Ports P11/PWM pin Register PMR1 PCR1 Bit Name PWM PCR11 Setting value Legend: X: Don't care. P10/TMOW pin Register PMR1 PCR1 Bit Name TMOW PCR10 Setting value ...

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Port 2 Port general I/O port also functioning as SCI3 I/O pins. Each pin of the port 2 is shown in figure 9.2. The register settings of PMR1and SCI3 have priority for functions of the pins ...

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Section 9 I/O Ports 9.2.2 Port Data Register 2 (PDR2) PDR2 is a general I/O port data register of port 2. Initial Bit Bit Name Value All 1 4 P24 0 3 P23 0 2 P22 0 ...

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Pin Functions The correspondence between the register specification and the port functions is shown below. P24 pin Register PCR2 Bit Name PCR24 Pin Function Setting Value 0 P24 input pin 1 P24 output pin P23 pin Register PCR2 Bit ...

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Section 9 I/O Ports P20/SCK3 pin Register SCR3 Bit Name CKE1 CKE0 Setting Value Legend: X: Don't care. Rev.5.00 Nov. 02, 2005 Page 118 of 500 REJ09B0027-0500 SMR PCR2 COM PCR20 Pin ...

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Port 3 Port general I/O port. Each pin of the port 3 is shown in figure 9.3. Port 3 has the following registers. Port control register 3 (PCR3) Port data register 3 (PDR3) 9.3.1 Port Control ...

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Section 9 I/O Ports 9.3.2 Port Data Register 3 (PDR3) PDR3 is a general I/O port data register of port 3. Initial Bit Bit Name Value 7 P37 0 6 P36 0 5 P35 0 4 P34 0 3 P33 ...

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P35 pin Register PCR3 Bit Name PCR35 Pin Function Setting Value 0 P35 input pin 1 P35 output pin P34 pin Register PCR3 Bit Name PCR34 Pin Function Setting Value 0 P34 input pin 1 P34 output pin P33 pin ...

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Section 9 I/O Ports P30 pin Register PCR3 Bit Name PCR30 Pin Function Setting Value 0 P30 input pin 1 P30 output pin 9.4 Port 5 Port general I/O port also functioning pin, and ...

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Port Mode Register 5 (PMR5) PMR5 switches the functions of pins in port 5. Initial Bit Bit Name Value 7 POF57 0 6 POF56 0 5 WKP5 0 4 WKP4 0 3 WKP3 0 2 WKP2 0 1 WKP1 ...

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Section 9 I/O Ports 9.4.2 Port Control Register 5 (PCR5) PCR5 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 5. Initial Bit Bit Name Value 7 PCR57 0 6 PCR56 0 5 ...

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Port Pull-Up Control Register 5 (PUCR5) PUCR5 controls the pull-up MOS in bit units of the pins set as the input ports. Initial Bit Bit Name Value 7, 6 All 0 5 PUCR55 0 4 PUCR54 0 3 PUCR53 ...

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Section 9 I/O Ports P56/SDA pin Register ICCR1 PCR5 Bit Name ICE PCR56 Setting Value Legend: X: Don't care. SDA performs the NMOS open-drain output, that enables a direct bus drive. P55/WKP5/ADTRG pin Register PMR5 ...

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P53/WKP3 pin Register PMR5 PCR5 Bit Name WKP3 PCR53 Setting Value Legend: X: Don't care. P52/WKP2 pin Register PMR5 PCR5 Bit Name WKP2 PCR52 Setting Value Legend: X: Don't care. ...

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Section 9 I/O Ports 9.5 Port 6 Port general I/O port also functioning as a timer Z I/O pin. Each pin of the port 6 is shown in figure 9.5. The register setting of the timer Z ...

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Port Data Register 6 (PDR6) PDR6 is a general I/O port data register of port 6. Initial Bit Bit Name Value 7 P67 0 6 P66 0 5 P65 0 4 P64 0 3 P63 0 2 P62 0 ...

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Section 9 I/O Ports P66/FTIOC1 pin Register TOER TFCR CMD1 and Bit Name EC1 CMD0 Setting Value Other than 00 Legend: X: Don't care. P65/FTIOB1 pin Register TOER TFCR CMD1 to Bit Name EB1 CMD0 Setting ...

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P64/FTIOA1 pin Register TOER TFCR CMD1 to Bit Name EB1 CMD0 Setting Value Legend: X: Don't care. P63/FTIOD0 pin Register TOER TFCR CMD1 to Bit Name ED0 CMD0 Setting Value Other than ...

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Section 9 I/O Ports P62/FTIOC0 pin Register TOER TFCR CMD1 to Bit Name EC0 CMD0 Setting Value Other than 00 Legend: X: Don't care. P61/FTIOB0 pin Register TOER TFCR CMD1 to Bit Name EB0 CMD0 Setting ...

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P60/FTIOA0 pin Register TOER TFCR CMD1 to Bit Name EA0 CMD0 Setting Value Legend: X: Don't care. TFCR TIORA0 PCR6 IOA2 to STCLK IOA0 PCR60 X 000 or 0 1XX 1 0 001 or X 01X ...

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Section 9 I/O Ports 9.6 Port 7 Port general I/O port also functioning as a timer V I/O pin and SCI3_2 I/O pin. Each pin of the port 7 is shown in figure 9.6. The register settings ...

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Port Data Register 7 (PDR7) PDR7 is a general I/O port data register of port 7. Initial Bit Bit Name Value P76 0 5 P75 0 4 P74 P72 0 1 P71 ...

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Section 9 I/O Ports P74/TMRIV pin Register PCR7 Bit Name PCR74 Pin Function Setting Value 0 P74 input/TMRIV input pin 1 P74 output/TMRIV input pin P72/TXD_2 pin Register PMR1 PCR7 Bit Name TXD2 PCR72 Setting Value ...

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Port 8 Port general I/O port. Each pin of the port 8 is shown in figure 9.7. Port 8 has the following registers. Port control register 8 (PCR8) Port data register 8 (PDR8) 9.7.1 Port Control ...

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Section 9 I/O Ports 9.7.3 Pin Functions The correspondence between the register specification and the port functions is shown below. P87 pin Register PCR8 Bit Name PCR87 Pin Function Setting Value 0 P87 input pin 1 P87 output pin P86 ...

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Port B Port input port also functioning as an A/D converter analog input pin. Each pin of the port B is shown in figure 9.8. Port B has the following register. Port data register B (PDRB) ...

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Section 9 I/O Ports Rev.5.00 Nov. 02, 2005 Page 140 of 500 REJ09B0027-0500 ...

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Section 10 Realtime Clock (RTC) The realtime clock (RTC timer used to count time ranging from a second to a week. Figure 10.1 shows the block diagram of the RTC. 10.1 Features Counts seconds, minutes, hours, and day-of-week ...

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Section 10 Realtime Clock (RTC) PSS 32-kHz oscillator 1/4 circuit TMOW [Legend] RTCCSR: Clock source select register RSECDR: Second date register/free running counter data register RMINDR: Minute date register RHRDR: Hour date register RWKDR: Day-of-week date register RTCCR1: RTC control ...

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Register Descriptions The RTC has the following registers. Second data register/free running counter data register (RSECDR) Minute data register (RMINDR) Hour data register (RHRDR) Day-of-week data register (RWKDR) RTC control register 1 (RTCCR1) RTC control register 2 (RTCCR2) Clock ...

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Section 10 Realtime Clock (RTC) 10.3.2 Minute Data Register (RMINDR) RMINDR counts the BCD-coded minute value on the carry generated once per minute by the RSECDR counting. The setting range is decimal 00 to 59. Initial Bit Bit Name Value ...

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Hour Data Register (RHRDR) RHRDR counts the BCD-coded hour value on the carry generated once per hour by RMINDR. The setting range is either decimal the selection of the 12/24 bit ...

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Section 10 Realtime Clock (RTC) 10.3.4 Day-of-Week Data Register (RWKDR) RWKDR counts the BCD-coded day-of-week value on the carry generated once per day by RHRDR. The setting range is decimal using bits WK2 to WK0. Initial Bit ...

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RTC Control Register 1 (RTCCR1) RTCCR1 controls start/stop and reset of the clock timer. For the definition of time expression, see figure 10.2. Initial Bit Bit Name Value 7 RUN — 6 12/24 — — 4 RST ...

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Section 10 Realtime Clock (RTC) 10.3.6 RTC Control Register 2 (RTCCR2) RTCCR2 controls RTC periodic interrupts of weeks, days, hours, minutes, and seconds. Enabling interrupts of weeks, days, hours, minutes, and seconds sets the IRRTA flag the ...

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Clock Source Select Register (RTCCSR) RTCCSR selects clock source. A free running counter controls start/stop of counter operation by the RUN bit in RTCCR1. When a clock other than 32.768 kHz is selected, the RTC is disabled and operates ...

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Section 10 Realtime Clock (RTC) 10.4 Operation 10.4.1 Initial Settings of Registers after Power-On The RTC registers that store second, minute, hour, and day-of week data are not reset by a RES input. Therefore, all registers must be set to ...

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Data Reading Procedure When the seconds, minutes, hours, or day-of-week datum is updated while time data is being read, the data obtained may not be correct, and so the time data must be read again. Figure 10.4 shows an ...

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Section 10 Realtime Clock (RTC) 10.5 Interrupt Source There are five kinds of RTC interrupts: week interrupts, day interrupts, hour interrupts, minute interrupts, and second interrupts. When using an interrupt, initiate the RTC last after other registers are set. Do ...

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Timer 8-bit timer that increments each time a clock pulse is input. This timer has two operating modes, interval and auto reload. Figure 11.1 shows a block diagram of timer B1. 11.1 Features Selection of seven internal ...

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Section 11 Timer B1 11.2 Input/Output Pin Table 11.1 shows the timer B1 pin configuration. Table 11.1 Pin Configuration Name Abbreviation Timer B1 event input TMIB1 11.3 Register Descriptions The timer B1 has the following registers. Timer mode register B1 ...

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Timer Mode Register B1 (TMB1) TMB1 selects the auto-reload function and input clock. Initial Bit Bit Name Value 7 TMB17 All 1 2 TMB12 0 1 TMB11 0 0 TMB10 0 11.3.2 Timer Counter B1 ...

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Section 11 Timer B1 11.3.3 Timer Load Register B1 (TLB1) TLB1 is an 8-bit write-only register for setting the reload value of TCB1. When a reload value is set in TLB1, the same value is loaded into TCB1 as well, ...

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Event Counter Operation Timer B1 can operate as an event counter in which TMIB1 is set to an event input pin. External event counting is selected by setting bits TMB12 to TMB10 in TMB1 to 1. TCB1 counts up ...

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Section 11 Timer B1 Rev.5.00 Nov. 02, 2005 Page 158 of 500 REJ09B0027-0500 ...

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Timer 8-bit timer based on an 8-bit counter. Timer V counts external events. Compare- match signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an ...

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Section 12 Timer V TRGV Clock select TMCIV PSS TMRIV TMOV [Legend] TCORA: Time constant register A TCORB: Time constant register B TCNTV: Timer counter V TCSRV: Timer control/status register V TCRV0: Timer control register V0 TCRV1: Timer control register ...

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Input/Output Pins Table 12.1 shows the timer V pin configuration. Table 12.1 Pin Configuration Name Timer V output Timer V clock input Timer V reset input Trigger input 12.3 Register Descriptions Time V has the following registers. Timer counter ...

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Section 12 Timer V TCORA and TCNTV are compared at all times. When the TCORA and TCNTV contents match, CMFA is set TCSRV. If CMIEA is also set TCRV0, a CPU interrupt is requested. ...

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Table 12.2 Clock Signals to Input to TCNTV and Counting Conditions TCRV0 Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 TCRV1 Bit 0 ICKS0 Description ...

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Section 12 Timer V 12.3.4 Timer Control/Status Register V (TCSRV) TCSRV indicates the status flag and controls outputs by using a compare match. Initial Bit Bit Name Value 7 CMFB 0 6 CMFA 0 5 OVF ...

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OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level for compare match A. The two output levels can be controlled independently. After a reset, the timer output is 0 until the ...

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Section 12 Timer V 12.4 Operation 12.4.1 Timer V Operation 1. According to table 12.2, six internal/external clock signals output by prescaler S can be selected as the timer V operating clock signals. When the operating clock signal is selected, ...

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