HD64F3684FP Renesas Electronics America, HD64F3684FP Datasheet - Page 314

• Manufacturer Part Number: HD64F3684FP
• Description: IC H8 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3684FP

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 16 Serial Communication Interface 3 (SCI3)
16.4.4
Figure 16.7 shows an example of operation for reception in asynchronous mode. In serial
reception, the SCI3 operates as described below.
1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs
2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive
5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
Table 16.6 shows the states of the SSR status flags and receive data handling when a receive error
is detected. If a receive error is detected, the RDRF flag retains its state before receiving data.
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER,
Rev.5.00 Nov. 02, 2005 Page 280 of 500
REJ09B0027-0500
Serial
data
RDRF
FER
LSI
operation
User
processing
internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this time, an
ERI interrupt request is generated. Receive data is not transferred to RDR.
RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated.
data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt
request is generated.
transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is
generated. Continuous reception is possible because the RXI interrupt routine reads the receive
data transferred to RDR before reception of the next receive data has been completed.
Serial Data Reception
1
Start
bit
Figure 16.7 Example of SCI3 Reception in Asynchronous Mode
0
D0
D1
Receive
1 frame
data
(8-Bit Data, Parity, One Stop Bit)
D7
Parity
0/1
bit
RXI request
Stop
bit
1
Start
bit
0
D0
RDRF
cleared to 0
RDR data read
1 frame
D1
Receive
data
D7
Parity
0/1
bit
Stop
bit
0
0 stop bit
detected
Mark state
(idle state)
1
ERI request in
response to
framing error
Framing error
processing