HD64F3684FP Renesas Electronics America, HD64F3684FP Datasheet - Page 392

IC H8 MCU FLASH 32K 64LQFP

HD64F3684FP

Manufacturer Part Number
HD64F3684FP
Description
IC H8 MCU FLASH 32K 64LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of HD64F3684FP

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Section 19 EEPROM
SDA
3. Sequential Read
Rev.5.00 Nov. 02, 2005 Page 358 of 500
REJ09B0027-0500
SCL
SCL
SDA
[Legend]
R/W: R/W code (0 is for a write and 1 is for a read),
ACK: acknowledge
This is a mode to read the data sequentially. Data is sequential read by either a current address
read or a random address read. If the EEPROM receives acknowledgement "0" after 1-byte
read data is output, the read address is incremented and the next 1-byte read data are coming
out. Data is output sequentially by incrementing addresses as long as the EEPROM receives
acknowledgement "0" after the data is output. The address will roll over and returns address
zero if it reaches the last address H'01FF. The sequential read can be continued after roll over.
The sequential read is terminated if the EEPROM receives acknowledgement "1" and a
following stop condition as the same manner as in the random address read.
The condition of a sequential read when the current address read is used is shown in figure
19.7.
condition
Start
[Legend]
R/W: R/W code (0 is for a write and 1 is for a read)
ACK: acknowledge
Figure 19.7 Sequential Read Operation (when current address read is used)
1
condition
Start
2
Slave address
1
3
4
2
5
6
3
Slave address
Figure 19.6 Random Address Read Operation
7
4
R/W ACK
8
9
5
Upper memory
A15
1
address
6
A8
8
7
ACK
9
R/W ACK
8
A7
lower memory
1
address
9
A0
8
1
D7
ACK
9
Read Data
condition
Start
1
8
D0
2
ACK
9
Slave address
3
4
· · · ·
5
6
D7
7
1
Read Data
R ACK
8
9
D7
Read Data
1
D0
8
ACK
9
D0
8
conditon
ACK
9
Stop
conditon
Stop

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