HD64F3684FP Renesas Electronics America, HD64F3684FP Datasheet - Page 363
HD64F3684FP
Manufacturer Part Number
HD64F3684FP
Description
IC H8 MCU FLASH 32K 64LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.HD64F3684GFPV.pdf
(538 pages)
Specifications of HD64F3684FP
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F3684FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F3684FPV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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17.4.7
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 17.16 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
processing
ICDRS
ICDRR
RDRF
(Input)
MST
TRS
SCL
SDA
User
SCL or SDA
input signal
Sampling
clock
Noise Canceler
[2] Set MST
(when outputting the clock)
Bit 0
Figure 17.16 Block Diagram of Noise Conceler
1
Figure 17.15 Receive Mode Operation Timing
Sampling clock
D
System clock
Data 1
period
Latch
Bit 1
C
2
Q
Bit 6
D
7
Latch
[3] Read ICDRR
C
Bit 7
8
Q
Bit 0
Data 2
1
Data 1
Rev.5.00 Nov. 02, 2005 Page 329 of 500
March detector
Section 17 I
Bit 6
7
Bit 7
2
C Bus Interface 2 (IIC2)
8
SCL or SDA
Internal
REJ09B0027-0500
signal
1
[3] Read ICDRR
Data 2
Data 3
Bit 0
2
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