HD64F3684FP Renesas Electronics America, HD64F3684FP Datasheet - Page 343

• Manufacturer Part Number: HD64F3684FP
• Description: IC H8 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3684FP

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

17.3.3
ICMR selects whether the MSB or LSB is transferred first, performs master mode wait control,
and selects the transfer bit count.
Bit
4
3
2
1
0
Bit
7
6
Bit Name
SDAOP
SCLO
IICRST
Bit Name
MLS
WAIT
I
2
C Bus Mode Register (ICMR)
Initial
Value
1
1
1
0
1
Initial
Value
0
0
R/W
R/W
R
R/W
R/W
R/W
R/W
Description
SDAO Write Protect
This bit controls change of output level of the SDA pin by
modifying the SDAO bit. To change the output level, clear
SDAO and SDAOP to 0 or set SDAO to 1 and clear
SDAOP to 0 by the MOV instruction. This bit is always
read as 1.
This bit monitors SCL output level. When SCLO is 1, SCL
pin outputs high. When SCLO is 0, SCL pin outputs low.
Reserved
This bit is always read as 1, and cannot be modified.
IIC Control Part Reset
This bit resets the control part except for I
this bit is set to 1 when hang-up occurs because of
communication failure during I
part can be reset without setting ports and initializing
registers.
Reserved
This bit is always read as 1, and cannot be modified.
Description
MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I
Wait Insertion Bit
In master mode with the I
whether to insert a wait after data transfer except the
acknowledge bit. When WAIT is set to 1, after the fall of
the clock for the final data bit, low period is extended for
two transfer clocks. If WAIT is cleared to 0, data and
acknowledge bits are transferred consecutively with no
wait inserted.
The setting of this bit is invalid in slave mode with the I
bus format or with the clocked synchronous serial format.
Rev.5.00 Nov. 02, 2005 Page 309 of 500
Section 17 I
2
2
C bus format, this bit selects
C bus format is used.
2
C operation, I
2
C Bus Interface 2 (IIC2)
REJ09B0027-0500
2
C registers. If
2
C control
2
C