MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 114

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Bus Operation
4.4.4.2 AUTOVECTOR INTERRUPT ACKNOWLEDGE CYCLE. When the interrupting
device cannot supply a vector number, it requests an automatically generated vector
(autovector). Instead of placing a vector number on the data bus and asserting DSACKx,
the device asserts AVEC to terminate the cycle. The DSACKx signals may not be asserted
4-38
* Internal arbitration may take between 0–2 clock cycles.
IACK7–IACK1
IRQ7–IRQ1
FC3–FC0
D23–D16
D31–D24
DSACKx
A31–A4
CLKO1
A3–A1
SIZ0
SIZ1
R/W
AS
DS
A0
Figure 4-27. Interrupt Acknowledge Cycle Timing
S0
Freescale Semiconductor, Inc.
S2
CYCLE
READ
For More Information On This Product,
S4
MC68360 USER’S MANUAL
Go to: www.freescale.com
S0
ARBITRATION
0–2 CLOCKS*
INTERNAL
VECTOR FROM 16-BIT PORT
VECTOR FROM 8-BIT PORT
INTERRUPT LEVEL
CPU SPACE
IACK CYCLE
1 BYTE
S1
S2
S4
S0
WRITE
STACK
S2