MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 122

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Bus Operation
4.5.3 Halt Operation
When HALT is asserted and BERR is not asserted, the QUICC halts external bus activity at
the next bus cycle boundary (see Figure 4-33). HALT by itself does not terminate a bus
cycle. HALT affects external bus cycles only; thus, a program that does not require use of
the external bus may continue executing until it requires use of the external bus.
Negating and reasserting HALT in accordance with the correct timing requirements provides
a single step (bus cycle to bus cycle) operation. The single-cycle mode allows the user to
proceed through (and debug) external QUICC operations, one bus cycle at a time. Since the
occurrence of a bus error while HALT is asserted causes a retry operation, the user must
anticipate retry cycles while debugging in the single-cycle mode. The single-step operation
and the software trace capability allow the system debugger to trace single bus cycles, sin-
gle instructions, or changes in program flow.
4-46
tire word access will be retried. This is true even if the relinquish
and retry was asserted on the second access and the first 8-bit
access was completed normally.
FC3–FC0
D31–D10
DSACKx
A31–A0
CLKO1
BERR
HALT
R/W
AS
DS
S0
Freescale Semiconductor, Inc.
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Figure 4-32. Late Retry Sequence
S2
WRITE
CYCLE
MC68360 USER’S MANUAL
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S4
HALT
S0
S2
RERUN
WRITE
S4