MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 177

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor, Inc.
CPU32+
available at the supervisor level, but execution of some instructions is not permitted at the
user level. There are separate SPs for each level. The S-bit in the SR indicates privilege
level and determines which SP is used for stack operations. The processor identifies each
bus access (supervisor or user mode) via function codes to enforce supervisor and user
access levels.
In a typical system, most programs execute at the user level. User programs can access
only their own code and data areas and are restricted from accessing other information. The
operating system executes at the supervisor privilege level, has access to all resources, per-
forms the overhead tasks for the user level programs, and coordinates their activities.
5.4.2.1 SUPERVISOR PRIVILEGE LEVEL. If the S-bit in the SR is set, supervisor privilege
level applies, and all instructions are executable. The bus cycles generated for instructions
executed in supervisor level are normally classified as supervisor references, and the values
of the function codes on FC2–FC0 refer to supervisor address spaces.
All exception processing is performed at the supervisor level. All bus cycles generated dur-
ing exception processing are supervisor references, and all stack accesses use the SSP.
Instructions that have important system effects can only be executed at supervisor level. For
instance, user programs are not permitted to execute STOP, LPSTOP, or RESET instruc-
tions. To prevent a user program from gaining privileged access, except in a controlled man-
ner, instructions that can alter the S-bit in the SR are privileged. The TRAP #n instruction
provides controlled user access to operating system services.
5.4.2.2 USER PRIVILEGE LEVEL. If the S-bit in the SR is cleared, the processor executes
instructions at the user privilege level. The bus cycles for an instruction executed at the user
privilege level are classified as user references, and the values of the function codes on
FC2–FC0 specify user address spaces. While the processor is at the user level, implicit ref-
erences to the system SP and explicit references to address register seven (A7) refer to the
USP.
5.4.2.3 CHANGING PRIVILEGE LEVEL. To change from user privilege level to supervisor
privilege level, a condition that causes exception processing must occur. When exception
processing begins, the current values in the SR, including the S-bit, are saved on the super-
visor stack, and then the S-bit is set to enable supervisor access. Execution continues at
supervisor privilege level until exception processing is complete.
To return to user access level, a system routine must execute one of the following instruc-
tions: MOVE to SR, ANDI to SR, EORI to SR, ORI to SR, or RTE. These instructions execute
only at supervisor privilege level and can modify the S-bit of the SR. After these instructions
execute, the instruction pipeline is flushed, then refilled from the appropriate address space.
The RTE instruction causes a return to a program that was executing when an exception
occurred. When RTE is executed, the exception stack frame saved on the supervisor stack
can be restored in either of two ways.
MC68360 USER’S MANUAL
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