MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 430

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Baud Rate Generators (BRGs)
desired parity mode. Changes in the parity mode may be accomplished in the UART proto-
col specific mode register (PSMR).
7.9.2 BRG Configuration Register (BRGC)
Each BRGC is a 24-bit, memory-mapped, read/write register that is cleared at reset. A reset
disables the BRG and puts the BRGO output clock to the high level. The BRGC can be writ-
ten at any time with no need to disable the SCCs or the external devices that are connected
to the BRGO output clock. The BRG changes will occur at the end of the next BRG clock
cycle (no spikes will occur on the BRGO output clock). The BRGC allows on-the-fly
changes. Two on-the-fly changes to the BRG should not occur within a time shorter than the
period of at least two BRG input clocks.
Bits 23–18—Reserved
7-106
CD10
23
11
The SCC associated with this BRG must be programmed to
UART mode. The SCC must have the TDCR and RDCR bits in
the general SCC mode register set to the 16 option for the au-
tobaud function to operate correctly.
The input clock that is supplied to the BRG in autobaud mode
should be as fast as possible to improve the accuracy of the start
bit measurement. Input frequencies such as 1.8432MHz,
3.68MHz, 7.36MHz and 14.72MHz should be used.
For autobaud to operate sucessfully, the SCC performing the
autobaud function must be connected to the baud rate generator
for that SCC. In other words, for SCC2 to correctly perform the
autobaud function, it must be clocked by BRG2. Also, for the
SCC to correctly detect an autobaud lock and an interrupt to be
generated, the SCC must receive three full Rx clocks from the
BRG before the autobaud process begins. To do this, first set
the GSMR with the ATB=0 and enable the BRG Rx clock to the
highest frequency. Immediately prior to the start of the autobaud
process (after device initialization) set the ATB bit equal to a
one.
CD9
22
10
CD8
21
Freescale Semiconductor, Inc.
9
For More Information On This Product,
—
CD7
20
8
MC68360 USER’S MANUAL
Go to: www.freescale.com
CD6
19
7
NOTES
CD5
18
6
RST
CD4
17
5
CD3
EN
16
4
EXTC1–EXTC0
CD2
15
3
CD1
14
2
ATB
CD0
13
1
CD11
DIV16
12
0