MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 273

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

MBAR can be written to using the following code. Address $0003FF00 in CPU space
(MBAR) will be loaded with the value $FFFF F001. This will set the base address of the inter-
nal registers to $FFFFF.
6.9.2 Module Base Address Register Enable (MBARE)
The MBARE is a 32-bit, memory-mapped, read-write register. Upon a total system reset, its
value may be read as $0. The address of this register is fixed at $03FF08 in CPU space. It
is used to enable the MBAR to be programmed when multiple QUICCs are in slave mode.
(See 6.8.1 MBAR in a Multiple QUICC System for details.)
MBS—MBAR Select
6.9.3 System Configuration and Protection Registers
The following paragraphs provide descriptions of the system configuration and protection
registers.
6.9.3.1 MODULE CONFIGURATION REGISTER (MCR). The MCR, which controls the
SIM60 configuration, can be read or written at any time.
RESET:
RESET:
MBS
31
15
—
0
0
MOVE
MOVEC
MOVEC
LEA
MOVES.L
MOVE
MOVEC
MOVEC
LEA
MOVE.L
MOVES.L
0 = No operation.
1 = The MBAR is now ready to be programmed on this slave QUICC device if the
30
14
—
—
0
0
MBARE pin was low during the write to this bit.
29
—
13
—
0
0
#7,D0
D0,SFC
D0,DFC
$3FF00,A0
(A0),D0
#7,D0
D0,SFC
D0,DFC
$3FF00,A0
#$FFFFF001,D0
D0,(A0)
28
12
—
—
0
0
Freescale Semiconductor, Inc.
27
—
11
—
0
0
For More Information On This Product,
26
10
—
—
0
0
MC68360 USER’S MANUAL
Go to: www.freescale.com
load D0 with the CPU space function code
load SFC to indicate CPU space
load DFC to indicate CPU space
load A0 with the address of MBAR
load D0 with the contents of MBAR
load D0 with the CPU space function code
load SFC to indicate CPU space
load DFC to indicate CPU space
load A0 with the address of MBAR
load D0 with the value to be written into MBAR
write the value contained in D0 into MBAR
25
—
—
0
9
0
24
—
—
0
8
0
23
—
—
0
7
0
22
—
—
0
6
0
21
—
—
System Integration Module (SIM60)
0
5
0
20
—
—
0
0
4
19
—
—
0
3
0
18
—
—
0
2
0
CPU SPACE ONLY
17
—
—
0
1
0
16
—
—
0
0
0