MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 734

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

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Applications
follow. (In embedded control applications, most users leave the CPU in supervisor mode
permanently.)
Step 3: Write the VBR
Many users initialize the ROM to contain an initial exception vector table. If so, the user
should write the CPU vector base register (VBR) to point to the starting location of the table.
(The exception vector table defines where to find the routines that handle interrupts, bus
errors, traps, etc.) Note, however, that exceptions will not be ready to be handled properly
until the stack pointer points to addressable RAM.
Step 4: Write the MBAR
The module base address register (MBAR), which always exists at a fixed address, deter-
mines where the 8-Kbyte block of QUICC internal RAM and internal peripherals are to be
mapped. To put the 8-Kbyte block at $700000, write $00700001 to the MBAR. The MBAR
must be accessed before any other QUICC internal peripheral or RAM location. Remember
that the MBAR must be written in a special way as described in the Section 6 System Inte-
gration Module (SIM60). (If multiple QUICCs exist in the system, it may be necessary to
write the MBARE before writing MBAR.)
Step 5: Verify a Dual-Port RAM Location
First, verify that the MBAR address was programmed correctly. This can be done by testing
one of the dual-port RAM locations. Write $33 and $CC to location $700000 and verify that
these values can be correctly read. Location $700000 is the beginning of the QUICC internal
RAM.
Step 6: Is This a Power-Up Reset?
Next, determine the cause of the reset from the reset status register (RSR). The RSR is nor-
mally cleared by the user after it is read (ones are written to RSR). If this is not a power-up
reset, the user may wish to take actions other than the ones listed or notify the system of the
cause of an unexpected reset to aid in debugging. Many of the following steps are only nec-
essary after a power-on reset. See Section 4 Bus Operation for more details on the effects
of the different types of resets.
Step 7: Deal with the Clock Synthesizer
The next step is to set up the clock synthesizer, which is located in the SIM60. The three
registers that control the clock synthesizer are the CLKOCR, the PLLCR, and the CDVCR.
If a low-speed external crystal is used (such as 32 kHz or 4 MHz), multiply the QUICC clock
frequency up to the desired speed (e.g., 25 MHz). If an external oscillator is used to provide
the exact system frequency, then this step is not needed.
The clock synthesizer has other options, such as SyncCLK and BRGCLK dividers, as well
as the ability to divide the general system clock frequency. These are used in low-power
applications. At this time, leave all these options in their default conditions. These options
should only be enabled when the rest of the application code is in a more stable state.
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MC68360 USER’S MANUAL
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