MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 754

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Applications
9.4.1.2 CLOCKING STRATEGY. In this application, the system clock is generated from a
25-MHz external oscillator into the QUICC. The MODCKx pins are configured for this. The
QUICC internal PLL then multiplies the frequency by 2, and outputs 25 MHz on CLKO1 (not
used) and 50 MHz on CLKO2 (with minimal skew between EXTAL, CLKO1, and CLKO2).
Minimal skew is very important in this application.
The oscillator is connected to the MC68EC040 BCLK, and the QUICC EXTAL and CLKO2
are connected to the MC68EC040 PCLK. Why not connect the oscillator to the QUICC
EXTAL pin and connect the QUICC CLKO1 to the MC68EC040 BCLK? The answer is that
the CLKO1 signal does not oscillate while the PLL is locking during power-on reset, and the
MC68EC040 needs continuous clocks, even during reset. (CLKO2, however, does oscillate
at the EXTAL frequency during power-on reset.) Thus, this solution provides continuous
clocks to the MC68EC040 at all times.
An external low-frequency crystal cannot be used in this design because the CLKO1 and
CLKO2 pins will stop oscillating while the PLL relocks, which would occur when the software
writes to the PLL to multiply the system frequency up to 25 MHz. This would violate the
MC68EC040 minimum operating frequency requirement of 16 MHz.
The QUICC clocking section allows for the clock oscillator to be kept running through the
VDDSYN pin in a power-down situation. Low-power modes should not be used in this design
due to the MC68EC040 requirement of a minimum operating frequency of 16 MHz.
9.4.1.3 RESET STRATEGY. If a QUICC is configured to provide the global chip select, it will
also provide an internal power-on reset generation. Thus, the RESET pin of the QUICC just
needs to be connected to the RSTI pin on the MC68EC040. The RSTO pin on the
MC68EC040 is not used in this design; thus, the MC68040 RESET instruction will have no
effect. (It could be added by using an external reset circuit to reset the MC68EC040 and to
connect the RSTO to the RESET pin on the QUICC through an open-drain gate.) If a push-
button switch is needed, it can be connected by an open-drain buffer to the hard reset
(RESETH) line, once debounced. The soft reset (RESETS) line is not used in this design. It
could be used to reset the QUICC without resetting the parallel I/O pins, chip selects, etc.
9.4.1.4 INTERRUPTS. External interrupts may be brought into the QUICC through either
the IRQx pins or parallel I/O pins. The QUICC prioritizes these interrupts with its own inter-
nally generated interrupts (e.g., timers) to obtain the current highest pending request. In
slave mode, the QUICC can output this request to another processor in the system.
The request can take the form of a single request pin (RQOUT) or three request pins
(IOUT2–IOUT0) that encode the priority of the request. Since the MC68EC040 uses
encoded inputs (IPL2–IPL0), the IOUT2–IOUT0 pins are chosen.
9-34
When the QUICC is in slave mode, the user should not use an
IRQx pin that is on an interrupt level occupied by either the CPM,
periodic interrupt timer, or sofware watchdog.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE