MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 801

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MC68EN360AI25VL

Manufacturer Part Number
MC68EN360AI25VL
Description
Manufacturer
Freescale
Datasheet

Specifications of MC68EN360AI25VL

Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
FQFP
Lead Free Status / RoHS Status
Compliant

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Applications
Figure 9-29 shows the interface to flash EPROM devices. In this design, the assumption is
made that only the MC68EC030 will access this array. The inverter is only required if DRAM
is used elsewhere in the system. This design assumes that the write operations are CE con-
trolled, rather than WE controlled. Most flash EPROM manufacturers now support this alter-
native timing method.
9-81
The QUICC CONFIG2–CONFIG0 pins are shown selecting
slave mode and a 32-bit port size for CS0. Thus, the CONFIG2–
CONFIG0 pins as shown are appropriate for the flash EPROM,
not the regular EPROM.
Figure 9-28. 128-Kbyte EPROM Bank—8 Bits Wide
D31–D24
CS0
SYSTEM BUS AND
QUICC-GENERATED SIGNALS
A16–A0
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
+5V
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE (Enable)
OE
P
PORT SIZE
128K 8
EPROM
27C010
BYTE
A10
A12
A13
A14
A15
A16
A11
A2
A4
A5
A6
A8
A9
A0
A1
A3
A7

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