MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 52

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Signal Descriptions
2-4
Clock and Test System Clock Out 1
Clock and Test
NOTE: I denotes input, 0 denotes output, and I/O is input/output.
(Cont'd)
System
Control
Group
Power
—
Table 2-1. System Bus Signal Index (Normal Operation)(Continued)
Soft Reset
Hard Reset
Halt
Bus Error
System Clock Out 2
Crystal Oscillator
External Filter Ca-
pacitor
Clock Mode Select
1–0
Instruction Fetch/
Development Serial
Input
Instruction Pipe 0/
Development Serial
Output
Instruction Pipe 1/
Row Address Select
1 Double-Drive
Breakpoint/
Development Serial
Clock
Freeze/Initial Config-
uration 2
Three-State
Test Clock
Test Mode Select
Test Data In
Test Data Out
Test Reset
Clock Synthesizer
Power
Clock Synthesizer
Ground
Clock Out Power
Clock Out Ground
Special Ground 1
Special Ground 2
System Power Sup-
ply and Return
No Connect
Signal Name
Freescale Semiconductor, Inc.
For More Information On This Product,
MODCK1–MODCK0 Selects the source of the internal system clock. (I) THESE
IPIPE1/RAS1DD
BKPT/DSCLK
IFETCH/DSI
IPIPE0/DSO
MC68360 USER’S MANUAL
Mnemonic
VCC, GND
NC4–NC1
CONFIG2
GNDSYN
FREEZE/
VCCSYN
GNDCLK
RESETS
RESETH
VCCCLK
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EXTAL,
GNDS1
GNDS2
CLKO1
CLKO2
BERR
HALT
XTAL
TRST
TRIS
TMS
TDO
XFC
TCK
TDI
)
Sft system reset. (open-drain I/O)
Hard system reset. (open-drain I/O)
Suspends external bus activity. (open-drain I/O)
Indicates an erroneous bus operation is being attempted.
(open-drain I/O)
Internal system clock output 1. (O)
Internal system clock output 2—normally 2x CLKO1. (O)
Connections for an external crystal to the internal oscillator
circuit. EXTAL (I), XTAL (O).
Connection pin for an external capacitor to filter the circuit of
the PLL (I).
PINS SHOULD NOT BE SET TO 00
Indicates when the CPU32+ is performing an instruction
word prefetch (O) or input to the CPU32+ background debug
mode (I).
Used to track movement of words through the instruction
pipeline (O) or output from the CPU32+ background debug
mode (O).
Used to track movement of words through the instruction
pipeline (O), or a row address select 1 “double-drive” output
(O).
Signals a hardware breakpoint to the QUICC (open-drain I/
O), or clock signal for CPU32+ background debug mode (I).
Indicates that the CPU32+ has acknowledged a breakpoint
(O), or initial QUICC configuration select (I).
Used to three-state all pins if QUICC is configured as a mas-
ter. Sampled during system reset. (I)
Provides a clock for Scan test logic. (I)
Controls test mode operations. (I)
Serial test instructions and test data signal. (I)
Serial test instructions and test data signal. (O)
Provides an asynchronous reset to the test controller. (I)
Power supply to the PLL of the clock synthesizer.
Ground supply to the PLL of the clock synthesizer.
Power supply to clock out pins.
Ground supply to clock out pins.
Special ground for fast AC timing on certain system bus sig-
nals.
Special ground for fast AC timing on certain system bus sig-
nals.
Power supply and return to the QUICC.
Four no-connect pins.
Function