MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 545

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

If just one of the TTx or TRx bits is set, the other half of the SCC can operate with another
protocol as programmed in the MODE bits of the GSMR. (This allows loopback modes to
DMA data from one memory location to another while converting the data to a specific serial
format.)
The SCC in transparent mode can work with the TSA or NMSI. The SCC can support
modem lines using the general-purpose I/O pins. The data can be transmitted and received
with MSB or LSB first in each octet.
The SCC in transparent mode consists of separate transmit and receive sections whose
operations are asynchronous with the CPU32+ core and may be either synchronous or
asynchronous with respect to the other SCCs. Each clock can be supplied from the internal
baud rate generator bank, DPLL output, or external pins.
7.10.21.1 TRANSPARENT CONTROLLER FEATURES. The transparent controller con-
tains the following key features:
7.10.21.2 TRANSPARENT CHANNEL FRAME TRANSMISSION PROCESSING. The
transparent transmitter is designed to work with almost no intervention from the CPU32+
core. When this CPU32+ core enables the SCC transmitter in transparent mode, it will start
transmitting idles. The SCC polls the first BD in the transmit channel’s BD table. When there
is a message to transmit, the SCC will fetch the data from memory, load the transmit FIFO,
and wait for transmitter synchronization before starting to transmit the message.
Transmitter synchronization can be achieved using the CTS pin or waiting for the receiver
to achieve synchronization, depending on the TXSY bit in the GSMR. See 7.10.21.4 Achiev-
ing Synchronization in Transparent Mode for more details. Once transmitter synchronization
is achieved, transmission begins.
When a BD’s data has been completely transmitted, the last in message (L) bit is checked.
If the L-bit is set, the SCC writes the message status bits into the BD and clears the R-bit. It
will then start transmitting idles until the next BD is ready. (Even if the next BD is already
ready, some idles will still be transmitted.) The transmitter will only begin transmission again
after it achieves synchronization.
• Flexible Data Buffers
• Automatic SYNC Detection on Receive
• CRCs Can Optionally Be Transmitted and Received
• Reverse Data Mode
• Another Protocol Can Be Performed on the SCC’s Other Half (Transmitter or Receiver)
• MC68302-Compatible Sync Options
—16-Bit Pattern
—8-Bit Pattern
—4-Bit Pattern
—External Sync Pin Support
During Transparent Mode
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Serial Communication Controllers (SCCs)