MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 537

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

F—First in Frame
CM—Continuous Mode
DE—DPLL Error
OV—Overrun
CD—Carrier Detect Lost
Data Length
Rx Data Buffer Pointer
7.10.20.13 BISYNC TRANSMIT BUFFER DESCRIPTOR (TX BD). Data is presented to
the CP for transmission on an SCC channel by arranging it in buffers referenced by the
channel’s Tx BD table. The CP confirms transmission or indicates error conditions using the
BDs to inform the processor that the buffers have been serviced.
This bit is set by the BISYNC controller when a DPLL error has occurred during the recep-
tion of this buffer. In decoding modes where a transition is promised every bit, the DPLL
error will be set when a missing transition has occurred.
A receiver overrun occurred during message reception.
The carrier detect signal was negated during message reception.
The data length is the number of octets that the CP has written into this BD’s data buffer,
including the BCS (if selected). In BISYNC mode, the data length should initially be set to
zero by the user; it is incremented each time a received character is written to the data
buffer.
The receive buffer pointer, which always points to the first location of the associated data
buffer, may be even or odd. The buffer may reside in either internal or external memory.
0 = The buffer is not the first in a frame.
1 = The buffer is the first in a frame
This bit is set by the transparent controller when this buffer is the first in a frame.
0 = The buffer is not the last in a frame.
1 = The buffer is the last in a frame
0 = Normal operation.
1 = The E-bit is not cleared by the CP after this BD is closed, allowing the associated
case one or more of the OV, CD, and DE bits are set. the transparent controller will
write the number of frame octets to the data length field.
data buffer to be overwritten automatically when the CP next accesses this BD.
However, the E-bit will be cleared if an error occurs during reception, regardless of
the CM bit.
The actual amount of memory allocated for this buffer should be
greater than or equal to the contents of the MRBLR.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
Serial Communication Controllers (SCCs)